81f6df323e
The irq delivery code has been rewritten. On entry to the irq vector the processor is switched to SVC32 mode so all interrupt routines now run in SVC32 mode rather than IRQ32 mode. This fixes lots of irq re-enabling problems. Interrupt latency times are now vastly improved for high priority interrupts. Cleaned up calling ast() before returning to USR32 mode (don't need to mess about with trapframe copying. Cleaned up all the comments and sorted out their indentation. Rewritten the soft interrupt delivery code. Added generic ARM7500 support rather than just RC7500 support. |
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iomd_clock.c | ||
iomd_fiq.S | ||
iomd_irq.S | ||
iomd_irqhandler.c | ||
iomdreg.h |