136 lines
6.5 KiB
C
136 lines
6.5 KiB
C
/* $NetBSD: imcreg.h,v 1.1 2001/09/10 14:13:31 rafal Exp $ */
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/*
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* Copyright (c) 2001 Rafal K. Boni
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARCH_SGIMIPS_DEV_IMCREG_H_
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#define _ARCH_SGIMIPS_DEV_IMCREG_H_
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#define IMC_CPUCTRL0 0x1fa00004 /* CPU control, register 0 */
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#define IMC_CPUCTRL0_REFMASK 0x0000000f /* # lines to refresh */
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#define IMC_CPUCTRL0_RFE 0x00000010 /* refresh enable */
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#define IMC_CPUCTRL0_GPR 0x00000020 /* GIO parity enable */
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#define IMC_CPUCTRL0_MPR 0x00000040 /* memory parity enable */
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#define IMC_CPUCTRL0_CPR 0x00000080 /* cpu bus parity enable */
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#define IMC_CPUCTRL0_WDOG 0x00000100 /* watchdog enable */
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#define IMC_CPUCTRL0_SIN 0x00000200 /* reset system */
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#define IMC_CPUCTRL0_GRR 0x00000400 /* graphics reset */
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#define IMC_CPUCTRL0_ENLOCK 0x00000800 /* enable EISA memory lock */
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#define IMC_CPUCTRL0_CMDPAR 0x00001000 /* SysCmd parity enable */
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#define IMC_CPUCTRL0_INTENA 0x00002000 /* enable CPU interrupts */
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#define IMC_CPUCTRL0_SNOOPENA 0x00004000 /* enable gfx DMA snoop */
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#define IMC_CPUCTRL0_PROM_WRENA 0x00008000 /* disable buserr on PROM
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* writes */
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#define IMC_CPUCTRL0_WRST 0x00010000 /* warm restart (reset cpu) */
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/* Bit 17 reserved 0x00020000 */
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#define IMC_CPUCTRL0_LITTLE 0x00040000 /* MC little-endian toggle */
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#define IMC_CPUCTRL0_WRRST 0x00080000 /* cpu warm reset */
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#define IMC_CPUCTRL0_MUXHWMSK 0x01f00000 /* MUX fifo high-water mask */
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#define IMC_CPUCTRL0_BADPAR 0x02000000 /* generate bad parity on
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* CPU->memory writes */
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#define IMC_CPUCTRL0_NCHKMEMPAR 0x04000000 /* disable CPU parity check
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* on memory reads. */
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#define IMC_CPUCTRL0_BACK2 0x08000000 /* enable back2back GIO wrt */
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#define IMC_CPUCTRL0_BUSRTMSK 0xf0000000 /* stall cycle for berr data */
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#define IMC_CPUCTRL1 0x1fa0000c /* CPU control, register 1 */
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#define IMC_CPUCTRL1_MCHWMSK 0x0000000f /* MC FIFO high water mask */
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#define IMC_CPUCTRL1_ABORTEN 0x00000010 /* Enable GIO bus timeouts */
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/* Bits 5 - 11 reserved 0x00000fe0 */
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#define IMC_CPUCTRL1_HPCFX 0x00001000 /* HPC endian fix */
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#define IMC_CPUCTRL1_HPCLITTLE 0x00002000 /* HPC DMA is little-endian */
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#define IMC_CPUCTRL1_EXP0FX 0x00004000 /* EXP0 endian fix */
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#define IMC_CPUCTRL1_EXP0LITTLE 0x00008000 /* EXP0 DMA is little-endian */
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#define IMC_CPUCTRL1_EXP1FX 0x00010000 /* EXP1 endian fix */
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#define IMC_CPUCTRL1_EXP1LITTLE 0x00020000 /* EXP1 DMA is little-endian */
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#define IMC_WDOG 0x1fa00014 /* Watchdog counter */
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#define IMC_WDOG_MASK 0x001fffff /* counter mask */
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#define IMC_SYSID 0x1fa0001c /* MC revision register */
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#define IMC_SYSID_REVMASK 0x0000000f /* MC revision mask */
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#define IMC_SYSID_HAVEISA 0x00000010 /* EISA present */
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#define IMC_RPSSDIV 0x1fa0002c /* RPSS divider */
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#define IMC_RPSSDIV_DIVMSK 0x000000ff /* RPC divider mask */
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#define IMC_RPSSDIV_INCMSK 0x0000ff00 /* RPC increment mask */
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#define IMC_EEPROM 0x1fa00034 /* EEPROM serial interface */
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/* Bit 1 is reserved 0x00000001 */
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#define IMC_EEPROM_CS 0x00000002 /* EEPROM chip select */
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#define IMC_EEPROM_SCK 0x00000004 /* EEPROM serial clock */
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#define IMC_EEPROM_SO 0x00000008 /* Serial data to EEPROM */
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#define IMC_EEPROM_SI 0x00000010 /* Serial data from EEPROM */
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#define IMC_CTRLD 0x1fa00044 /* Refresh counter preload */
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#define IMC_CTRLD_MSK 0x000000ff /* Counter preload mask */
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#define IMC_REFCTR 0x1fa0004c /* Refresh counter */
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#define IMC_REFCTR_MSK 0x000000ff /* Refresh counter mask */
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#define IMC_GIO64ARB 0x1fa00084 /* GIO64 arbitration params */
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#define IMC_GIO64ARB_HPC64 0x00000001 /* HPC addr size (32/64bit) */
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#define IMC_GIO64ARB_GRX64 0x00000002 /* Gfx addr size (32/64bit) */
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#define IMC_GIO64ARB_EXP064 0x00000004 /* EXP0 addr size (32/64bit) */
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#define IMC_GIO64ARB_EXP164 0x00000008 /* EXP0 addr size (32/64bit) */
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#define IMC_GIO64ARB_EISA64 0x00000010 /* EISA addr size (32/64bit) */
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#define IMC_GIO64ARB_HPCEXP64 0x00000020 /* HPC2 addr size (32/64bit) */
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#define IMC_GIO64ARB_GRXRT 0x00000040 /* Gfx is realtime device */
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#define IMC_GIO64ARB_EXP0RT 0x00000080 /* EXP0 is realtime device */
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#define IMC_GIO64ARB_EXP1RT 0x00000100 /* EXP1 is realtime device */
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#define IMC_GIO64ARB_EISAMST 0x00000200 /* EISA can be busmaster */
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#define IMC_GIO64ARB_ONEGIO 0x00000400 /* One one GIO64 bus */
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#define IMC_GIO64ARB_GRXMST 0x00000800 /* Gfx can be busmaster */
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#define IMC_GIO64ARB_EXP0MST 0x00001000 /* EXP0 can be busmaster */
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#define IMC_GIO64ARB_EXP1MST 0x00002000 /* EXP1 can be busmaster */
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#define IMC_GIO64ARB_EXP0PIPE 0x00004000 /* EXP0 is pipelined */
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#define IMC_GIO64ARB_EXP1PIPE 0x00008000 /* EXP1 is pipelined */
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#define IMC_CPUTIME 0x1fa0008c /* Arbiter CPU time period */
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#define IMC_LBTIME 0x1fa0009c /* Arbiter long-burst time */
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#define IMC_MEMCFG0 0x1fa000c4 /* Mem config, regsiter 0 */
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#define IMC_MEMCFG1 0x1fa000cc /* Mem config, regsiter 1 */
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#define IMC_CPU_MEMACC 0x1fa000d4 /* CPU mem access config */
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#define IMC_GIO_MEMACC 0x1fa000dc /* GIO mem access config */
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#define IMC_CPU_ERRADDR 0x1fa000e4 /* CPU error address */
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#define IMC_CPU_ERRSTAT 0x1fa000ec /* CPU error status */
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#define IMC_GIO_ERRADDR 0x1fa000f4 /* GIO error address */
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#define IMC_GIO_ERRSTAT 0x1fa000fc /* GIO error status */
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#endif /* _ARCH_SGIMIPS_DEV_IMCREG_H_ */
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