85 lines
3.0 KiB
C
85 lines
3.0 KiB
C
/* $NetBSD: tx39spireg.h,v 1.1 1999/11/20 19:56:37 uch Exp $ */
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/*
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Toshiba TX3912/3922 SPI module
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*/
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#define TX39_SPICTRL_REG 0x160
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#define TX39_SPITXHOLD_REG 0x164 /* W */
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#define TX39_SPIRXHOLD_REG 0x164 /* R */
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/*
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* SPI Control Register
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*/
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/* R */
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#define TX39_SPICTRL_SPION 0x00020000
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#define TX39_SPICTRL_EMPTY 0x00010000
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/* R/W */
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#define TX39_SPICTRL_DELAYVAL_SHIFT 12
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#define TX39_SPICTRL_DELAYVAL_MASK 0xf
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#define TX39_SPICTRL_DELAYVAL(cr) \
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(((cr) >> TX39_SPICTRL_DELAYVAL_SHIFT) & \
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TX39_SPICTRL_DELAYVAL_MASK)
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#define TX39_SPICTRL_DELAYVAL_SET(cr, val) \
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((cr) | (((val) << TX39_SPICTRL_DELAYVAL_SHIFT) & \
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(TX39_SPICTRL_DELAYVAL_MASK << TX39_SPICTRL_DELAYVAL_SHIFT)))
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/* SPICLK Rate = 7.3728MHz/(BAUDRATE*2 + 2) */
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#define TX39_SPICTRL_BAUDRATE_SHIFT 8
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#define TX39_SPICTRL_BAUDRATE_MASK 0xf
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#define TX39_SPICTRL_BAUDRATE(cr) \
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(((cr) >> TX39_SPICTRL_BAUDRATE_SHIFT) & \
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TX39_SPICTRL_BAUDRATE_MASK)
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#define TX39_SPICTRL_BAUDRATE_SET(cr, val) \
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((cr) | (((val) << TX39_SPICTRL_BAUDRATE_SHIFT) & \
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(TX39_SPICTRL_BAUDRATE_MASK << TX39_SPICTRL_BAUDRATE_SHIFT)))
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#define TX39_SPICTRL_PHAPOL 0x00000020
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#define TX39_SPICTRL_CLKPOL 0x00000010
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#define TX39_SPICTRL_WORD 0x00000004
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#define TX39_SPICTRL_LSB 0x00000002
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#define TX39_SPICTRL_ENSPI 0x00000001
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/*
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* SPI Transmitter Holding Register
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*/
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/* W */
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#define TX39_SPICTRL_TXDATA_SHIFT 0
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#define TX39_SPICTRL_TXDATA_MASK 0xffff
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#define TX39_SPICTRL_TXDATA_SET(cr, val) \
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((cr) | (((val) << TX39_SPICTRL_TXDATA_SHIFT) & \
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(TX39_SPICTRL_TXDATA_MASK << TX39_SPICTRL_TXDATA_SHIFT)))
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/*
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* SPI Receiver Holding Register
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*/
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/* R */
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#define TX39_SPICTRL_RXDATA_SHIFT 8
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#define TX39_SPICTRL_RXDATA_MASK 0xf
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#define TX39_SPICTRL_RXDATA(cr) \
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(((cr) >> TX39_SPICTRL_RXDATA_SHIFT) & \
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TX39_SPICTRL_RXDATA_MASK)
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