518 lines
20 KiB
C
518 lines
20 KiB
C
/* $NetBSD: tx39biureg.h,v 1.2 1999/12/31 16:07:29 uch Exp $ */
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/*
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* Copyright (c) 1999, 2000, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* Toshiba TX3912/3922 BIU module (Bus Interface Unit)
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*/
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/*
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* System Address Map
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*/
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#define TX39_SYSADDR_DRAMBANK0CS1 0x00000000
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#define TX39_SYSADDR_DRAMBANK1CS1 0x02000000
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#define TX39_SYSADDR_DRAMBANK0 0x04000000
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#define TX39_SYSADDR_DRAMBANK1 0x06000000
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#define TX39_SYSADDR_DRAMBANK_LEN 0x02000000
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#define TX39_SYSADDR_CARD1 0x08000000
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#define TX39_SYSADDR_CARD2 0x0C000000
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/* 64MByte */
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#define TX39_SYSADDR_CARD_SIZE 0x04000000
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#define TX39_SYSADDR_CS1 0x10000000
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#define TX39_SYSADDR_CS2 0x10400000
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#define TX39_SYSADDR_CS3 0x10800000
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/* 4MByte */
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#define TX39_SYSADDR_CS_SIZE 0x00400000
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#define TX39_SYSADDR_CONFIG_REG 0x10c00000
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#define TX39_SYSADDR_CONFIG_REG_LEN 0x00200000
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#define TX39_SYSADDR_SDRAMBANK0MODE_REG 0x10e00000
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#define TX39_SYSADDR_SDRAMBANK1MODE_REG 0x10f00000
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#define TX39_SYSADDR_CS0 0x11000000
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#define TX39_SYSADDR_KUSEG_DRAMBANK0CS1 0x40000000
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#define TX39_SYSADDR_KUSEG_DRAMBANK1CS1 0x42000000
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#define TX39_SYSADDR_KUSEG_DRAMBANK0 0x44000000
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#define TX39_SYSADDR_KUSEG_DRAMBANK1 0x46000000
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#define TX39_SYSADDR_KUSEG_CS0 0x50000000
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#define TX39_SYSADDR_KUSEG_CS1 0x58000000
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#define TX39_SYSADDR_KUSEG_CS2 0x5c000000
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#define TX39_SYSADDR_KUSEG_CS3 0x60000000
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#define TX39_SYSADDR_CARD1MEM 0x64000000
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#define TX39_SYSADDR_CARD2MEM 0x68000000
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#define TX39_SYSADDR_MCS0 0x6c000000
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#define TX39_SYSADDR_MCS1 0x70000000
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#ifdef TX391X
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#define TX39_SYSADDR_MCS2 0x74000000
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#define TX39_SYSADDR_MCS3 0x78000000
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#endif /* TX391X */
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/* 64MByte */
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#define TX39_SYSADDR_MCS_SIZE 0x04000000
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/*
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* BIU module registers.
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*/
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#define TX39_MEMCONFIG0_REG 0x00
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#define TX39_MEMCONFIG1_REG 0x04
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#define TX39_MEMCONFIG2_REG 0x08
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#define TX39_MEMCONFIG3_REG 0x0C
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#define TX39_MEMCONFIG4_REG 0x10
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#define TX39_MEMCONFIG5_REG 0x14
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#define TX39_MEMCONFIG6_REG 0x18
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#define TX39_MEMCONFIG7_REG 0x1C
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#define TX39_MEMCONFIG8_REG 0x20
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/*
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* Memory Configuration 0 Register
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*/
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/* R/W */
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#define TX39_MEMCONFIG0_ENDCLKOUTTRI 0x40000000
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#define TX39_MEMCONFIG0_DISDQMINIT 0x20000000
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#define TX39_MEMCONFIG0_ENSDRAMPD 0x10000000
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#define TX39_MEMCONFIG0_SHOWDINO 0x08000000
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#define TX39_MEMCONFIG0_ENRMAP2 0x04000000
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#define TX39_MEMCONFIG0_ENRMAP1 0x02000000
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#define TX39_MEMCONFIG0_ENWRINPAGE 0x01000000
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#define TX39_MEMCONFIG0_ENCS3USER 0x00800000
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#define TX39_MEMCONFIG0_ENCS2USER 0x00400000
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#define TX39_MEMCONFIG0_ENCS1USER 0x00200000
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#define TX39_MEMCONFIG0_ENCS1DRAM 0x00100000
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#define TX39_MEMCONFIG0_BANK1CONF_SHIFT 18
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#define TX39_MEMCONFIG0_BANK1CONF_MASK 0x3
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#define TX39_MEMCONFIG0_BANK1CONF(cr) \
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(((cr) >> TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \
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TX39_MEMCONFIG0_BANK1CONF_MASK)
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#define TX39_MEMCONFIG0_BANK1CONF_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_BANK1CONF_SHIFT) & \
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(TX39_MEMCONFIG0_BANK1CONF_MASK << TX39_MEMCONFIG0_BANK1CONF_SHIFT)))
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#define TX39_MEMCONFIG0_BANK0CONF_SHIFT 16
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#define TX39_MEMCONFIG0_BANK0CONF_MASK 0x3
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#define TX39_MEMCONFIG0_BANK0CONF(cr) \
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(((cr) >> TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \
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TX39_MEMCONFIG0_BANK0CONF_MASK)
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#define TX39_MEMCONFIG0_BANK0CONF_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_BANK0CONF_SHIFT) & \
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(TX39_MEMCONFIG0_BANK0CONF_MASK << TX39_MEMCONFIG0_BANK0CONF_SHIFT)))
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#define TX39_MEMCONFIG0_BANKCONF_16BITSDRAM 0x3
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#define TX39_MEMCONFIG0_BANKCONF_8BITSDRAM 0x2
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#define TX39_MEMCONFIG0_BANKCONF_32BITSDHDRAM 0x1
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#define TX39_MEMCONFIG0_BANKCONF_16BITSDHDRAM 0x0
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#define TX39_MEMCONFIG0_ROWSEL1_SHIFT 14
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#define TX39_MEMCONFIG0_ROWSEL1_MASK 0x3
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#define TX39_MEMCONFIG0_ROWSEL1(cr) \
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(((cr) >> TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \
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TX39_MEMCONFIG0_ROWSEL1_MASK)
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#define TX39_MEMCONFIG0_ROWSEL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL1_SHIFT) & \
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(TX39_MEMCONFIG0_ROWSEL1_MASK << TX39_MEMCONFIG0_ROWSEL1_SHIFT)))
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#define TX39_MEMCONFIG0_ROWSEL0_SHIFT 12
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#define TX39_MEMCONFIG0_ROWSEL0_MASK 0x3
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#define TX39_MEMCONFIG0_ROWSEL0(cr) \
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(((cr) >> TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \
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TX39_MEMCONFIG0_ROWSEL0_MASK)
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#define TX39_MEMCONFIG0_ROWSEL0_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_ROWSEL0_SHIFT) & \
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(TX39_MEMCONFIG0_ROWSEL0_MASK << TX39_MEMCONFIG0_ROWSEL0_SHIFT)))
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#define TX39_MEMCONFIG0_COLSEL1_SHIFT 8
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#define TX39_MEMCONFIG0_COLSEL1_MASK 0xf
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#define TX39_MEMCONFIG0_COLSEL1(cr) \
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(((cr) >> TX39_MEMCONFIG0_COLSEL1_SHIFT) & \
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TX39_MEMCONFIG0_COLSEL1_MASK)
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#define TX39_MEMCONFIG0_COLSEL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_COLSEL1_SHIFT) & \
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(TX39_MEMCONFIG0_COLSEL1_MASK << TX39_MEMCONFIG0_COLSEL1_SHIFT)))
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#define TX39_MEMCONFIG0_COLSEL0_SHIFT 4
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#define TX39_MEMCONFIG0_COLSEL0_MASK 0xf
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#define TX39_MEMCONFIG0_COLSEL0(cr) \
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(((cr) >> TX39_MEMCONFIG0_COLSEL0_SHIFT) & \
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TX39_MEMCONFIG0_COLSEL0_MASK)
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#define TX39_MEMCONFIG0_COLSEL0_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG0_COLSEL0_SHIFT) & \
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(TX39_MEMCONFIG0_COLSEL0_MASK << TX39_MEMCONFIG0_COLSEL0_SHIFT)))
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#define TX39_MEMCONFIG0_CS3SIZE 0x00000008
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#define TX39_MEMCONFIG0_CS2SIZE 0x00000004
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#define TX39_MEMCONFIG0_CS1SIZE 0x00000002
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#define TX39_MEMCONFIG0_CS0SIZE 0x00000001
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/*
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* Memory Configuration 1 Register
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*/
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#ifdef TX391X
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#define TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT 28
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#define TX39_MEMCONFIG1_MCS3ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG1_MCS3ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG1_MCS3ACCVAL1_MASK)
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#define TX39_MEMCONFIG1_MCS3ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG1_MCS3ACCVAL1_MASK << TX39_MEMCONFIG1_MCS3ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT 24
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#define TX39_MEMCONFIG1_MCS3ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG1_MCS3ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG1_MCS3ACCVAL2_MASK)
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#define TX39_MEMCONFIG1_MCS3ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG1_MCS3ACCVAL2_MASK << TX39_MEMCONFIG1_MCS3ACCVAL2_SHIFT)))
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#define TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT 20
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#define TX39_MEMCONFIG1_MCS2ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG1_MCS2ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG1_MCS2ACCVAL1_MASK)
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#define TX39_MEMCONFIG1_MCS2ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG1_MCS2ACCVAL1_MASK << TX39_MEMCONFIG1_MCS2ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT 16
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#define TX39_MEMCONFIG1_MCS2ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG1_MCS2ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG1_MCS2ACCVAL2_MASK)
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#define TX39_MEMCONFIG1_MCS2ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG1_MCS2ACCVAL2_MASK << TX39_MEMCONFIG1_MCS2ACCVAL2_SHIFT)))
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_MEMCONFIG1_C48MPLLON 0x40000000
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#define TX39_MEMCONFIG1_ENMCS1BE 0x20000000
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#define TX39_MEMCONFIG1_ENMCS0BE 0x10000000
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#define TX39_MEMCONFIG1_ENMCS1ACC 0x08000000
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#define TX39_MEMCONFIG1_ENMCS0ACC 0x04000000
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#define TX39_MEMCONFIG1_BCLKDIV_SHIFT 23
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#define TX39_MEMCONFIG1_BCLKDIV_MASK 0x7
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#define TX39_MEMCONFIG1_BCLKDIV(cr) \
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(((cr) >> TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \
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TX39_MEMCONFIG1_BCLKDIV_MASK)
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#define TX39_MEMCONFIG1_BCLKDIV_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_BCLKDIV_SHIFT) & \
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(TX39_MEMCONFIG1_BCLKDIV_MASK << TX39_MEMCONFIG1_BCLKDIV_SHIFT)))
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#define TX39_MEMCONFIG1_ENBCLK 0x00400000
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#define TX39_MEMCONFIG1_ENMCS1PAGE 0x00200000
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#define TX39_MEMCONFIG1_ENMCS0PAGE 0x00100000
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#define TX39_MEMCONFIG1_ENMCS1WAIT 0x00080000
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#define TX39_MEMCONFIG1_ENMCS0WAIT 0x00040000
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#define TX39_MEMCONFIG1_MCS1_32 0x00020000
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#define TX39_MEMCONFIG1_MCS0_32 0x00010000
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#endif /* TX392X */
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#define TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT 12
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#define TX39_MEMCONFIG1_MCS1ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG1_MCS1ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG1_MCS1ACCVAL1_MASK)
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#define TX39_MEMCONFIG1_MCS1ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG1_MCS1ACCVAL1_MASK << TX39_MEMCONFIG1_MCS1ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT 8
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#define TX39_MEMCONFIG1_MCS1ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG1_MCS1ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG1_MCS1ACCVAL2_MASK)
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#define TX39_MEMCONFIG1_MCS1ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG1_MCS1ACCVAL2_MASK << TX39_MEMCONFIG1_MCS1ACCVAL2_SHIFT)))
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#define TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT 4
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#define TX39_MEMCONFIG1_MCS0ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG1_MCS0ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG1_MCS0ACCVAL1_MASK)
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#define TX39_MEMCONFIG1_MCS0ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG1_MCS0ACCVAL1_MASK << TX39_MEMCONFIG1_MCS0ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT 0
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#define TX39_MEMCONFIG1_MCS0ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG1_MCS0ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG1_MCS0ACCVAL2_MASK)
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#define TX39_MEMCONFIG1_MCS0ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG1_MCS0ACCVAL2_MASK << TX39_MEMCONFIG1_MCS0ACCVAL2_SHIFT)))
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/*
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* Memory Configuration 2 Register
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*/
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/* Define access timing. not required yet */
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#define TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT 28
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#define TX39_MEMCONFIG2_CS3ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG2_CS3ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG2_CS3ACCVAL1_MASK)
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#define TX39_MEMCONFIG2_CS3ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG2_CS3ACCVAL1_MASK << TX39_MEMCONFIG2_CS3ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT 24
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#define TX39_MEMCONFIG2_CS3ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG2_CS3ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG2_CS3ACCVAL2_MASK)
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#define TX39_MEMCONFIG2_CS3ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG2_CS3ACCVAL2_MASK << TX39_MEMCONFIG2_CS3ACCVAL2_SHIFT)))
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#define TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT 20
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#define TX39_MEMCONFIG2_CS2ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG2_CS2ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG2_CS2ACCVAL1_MASK)
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#define TX39_MEMCONFIG2_CS2ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG2_CS2ACCVAL1_MASK << TX39_MEMCONFIG2_CS2ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT 16
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#define TX39_MEMCONFIG2_CS2ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG2_CS2ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG2_CS2ACCVAL2_MASK)
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#define TX39_MEMCONFIG2_CS2ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG2_CS2ACCVAL2_MASK << TX39_MEMCONFIG2_CS2ACCVAL2_SHIFT)))
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#define TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT 12
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#define TX39_MEMCONFIG2_CS1ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG2_CS1ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG2_CS1ACCVAL1_MASK)
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#define TX39_MEMCONFIG2_CS1ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG2_CS1ACCVAL1_MASK << TX39_MEMCONFIG2_CS1ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT 8
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#define TX39_MEMCONFIG2_CS1ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG2_CS1ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG2_CS1ACCVAL2_MASK)
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#define TX39_MEMCONFIG2_CS1ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG2_CS1ACCVAL2_MASK << TX39_MEMCONFIG2_CS1ACCVAL2_SHIFT)))
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#define TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT 4
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#define TX39_MEMCONFIG2_CS0ACCVAL1_MASK 0xf
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#define TX39_MEMCONFIG2_CS0ACCVAL1(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \
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TX39_MEMCONFIG2_CS0ACCVAL1_MASK)
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#define TX39_MEMCONFIG2_CS0ACCVAL1_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT) & \
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(TX39_MEMCONFIG2_CS0ACCVAL1_MASK << TX39_MEMCONFIG2_CS0ACCVAL1_SHIFT)))
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#define TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT 0
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#define TX39_MEMCONFIG2_CS0ACCVAL2_MASK 0xf
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#define TX39_MEMCONFIG2_CS0ACCVAL2(cr) \
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(((cr) >> TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \
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TX39_MEMCONFIG2_CS0ACCVAL2_MASK)
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#define TX39_MEMCONFIG2_CS0ACCVAL2_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT) & \
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(TX39_MEMCONFIG2_CS0ACCVAL2_MASK << TX39_MEMCONFIG2_CS0ACCVAL2_SHIFT)))
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/*
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* Memory Configuration 3 Register
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*/
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/* Define access timing, enable read page mode, PC-Card. */
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#define TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT 28
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#define TX39_MEMCONFIG3_CARD2ACCVAL_MASK 0xf
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#define TX39_MEMCONFIG3_CARD2ACCVAL(cr) \
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(((cr) >> TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \
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TX39_MEMCONFIG3_CARD2ACCVAL_MASK)
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#define TX39_MEMCONFIG3_CARD2ACCVAL_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT) & \
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(TX39_MEMCONFIG3_CARD2ACCVAL_MASK << TX39_MEMCONFIG3_CARD2ACCVAL_SHIFT)))
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#define TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT 24
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#define TX39_MEMCONFIG3_CARD1ACCVAL_MASK 0xf
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#define TX39_MEMCONFIG3_CARD1ACCVAL(cr) \
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(((cr) >> TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \
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TX39_MEMCONFIG3_CARD1ACCVAL_MASK)
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#define TX39_MEMCONFIG3_CARD1ACCVAL_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT) & \
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(TX39_MEMCONFIG3_CARD1ACCVAL_MASK << TX39_MEMCONFIG3_CARD1ACCVAL_SHIFT)))
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#define TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT 20
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#define TX39_MEMCONFIG3_CARD2IOACCVAL_MASK 0xf
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#define TX39_MEMCONFIG3_CARD2IOACCVAL(cr) \
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(((cr) >> TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \
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TX39_MEMCONFIG3_CARD2IOACCVAL_MASK)
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#define TX39_MEMCONFIG3_CARD2IOACCVAL_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT) & \
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(TX39_MEMCONFIG3_CARD2IOACCVAL_MASK << TX39_MEMCONFIG3_CARD2IOACCVAL_SHIFT)))
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#define TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT 16
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#define TX39_MEMCONFIG3_CARD1IOACCVAL_MASK 0xf
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#define TX39_MEMCONFIG3_CARD1IOACCVAL(cr) \
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(((cr) >> TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \
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TX39_MEMCONFIG3_CARD1IOACCVAL_MASK)
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#define TX39_MEMCONFIG3_CARD1IOACCVAL_SET(cr, val) \
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((cr) | (((val) << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT) & \
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(TX39_MEMCONFIG3_CARD1IOACCVAL_MASK << TX39_MEMCONFIG3_CARD1IOACCVAL_SHIFT)))
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#ifdef TX391X
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#define TX39_MEMCONFIG3_ENMCS3PAGE 0x00008000
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#define TX39_MEMCONFIG3_ENMCS2PAGE 0x00004000
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#define TX39_MEMCONFIG3_ENMCS1PAGE 0x00002000
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#define TX39_MEMCONFIG3_ENMCS0PAGE 0x00001000
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#endif /* TX391X */
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#define TX39_MEMCONFIG3_ENCS3PAGE 0x00000800
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#define TX39_MEMCONFIG3_ENCS2PAGE 0x00000400
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#define TX39_MEMCONFIG3_ENCS1PAGE 0x00000200
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#define TX39_MEMCONFIG3_ENCS0PAGE 0x00000100
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#define TX39_MEMCONFIG3_CARD2WAITEN 0x00000080
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#define TX39_MEMCONFIG3_CARD1WAITEN 0x00000040
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#define TX39_MEMCONFIG3_CARD2IOEN 0x00000020
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#define TX39_MEMCONFIG3_CARD1IOEN 0x00000010
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#ifdef TX391X
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#define TX39_MEMCONFIG3_PORT8SEL 0x00000008
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#endif /* TX391X */
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#ifdef TX392X
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#define TX39_MEMCONFIG3_CARD2_8SEL 0x00000008
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#define TX39_MEMCONFIG3_CARD1_8SEL 0x00000004
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#endif /* TX392X */
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/*
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* Memory Configuration 4 Register
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|
*/
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/* DMA */
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#define TX39_MEMCONFIG4_ENBANK1HDRAM 0x80000000
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#define TX39_MEMCONFIG4_ENBANK0HDRAM 0x40000000
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#define TX39_MEMCONFIG4_ENARB 0x20000000
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#define TX39_MEMCONFIG4_DISSNOOP 0x10000000
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#define TX39_MEMCONFIG4_CLRWRBUSERRINT 0x08000000
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|
#define TX39_MEMCONFIG4_ENBANK1OPT 0x04000000
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|
#define TX39_MEMCONFIG4_ENBANK0OPT 0x02000000
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|
#define TX39_MEMCONFIG4_ENWATCH 0x01000000
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|
|
|
/*
|
|
* WatchDogTimerRate = (WATCHTIME[3:0] + 1) * 64 / 36.864MHz
|
|
*/
|
|
#define TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT 20
|
|
#define TX39_MEMCONFIG4_WATCHTIMEVAL_MASK 0xf
|
|
#define TX39_MEMCONFIG4_WATCHTIMEVAL(cr) \
|
|
(((cr) >> TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \
|
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TX39_MEMCONFIG4_WATCHTIMEVAL_MASK)
|
|
#define TX39_MEMCONFIG4_WATCHTIMEVAL_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT) & \
|
|
(TX39_MEMCONFIG4_WATCHTIMEVAL_MASK << TX39_MEMCONFIG4_WATCHTIMEVAL_SHIFT)))
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|
|
|
|
|
#define TX39_MEMCONFIG4_MEMPOWERDOWN 0x00010000
|
|
#define TX39_MEMCONFIG4_ENRFSH1 0x00008000
|
|
#define TX39_MEMCONFIG4_ENRFSH0 0x00004000
|
|
|
|
#define TX39_MEMCONFIG4_RFSHVAL1_SHIFT 8
|
|
#define TX39_MEMCONFIG4_RFSHVAL1_MASK 0x3f
|
|
#define TX39_MEMCONFIG4_RFSHVAL1(cr) \
|
|
(((cr) >> TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \
|
|
TX39_MEMCONFIG4_RFSHVAL1_MASK)
|
|
#define TX39_MEMCONFIG4_RFSHVAL1_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL1_SHIFT) & \
|
|
(TX39_MEMCONFIG4_RFSHVAL1_MASK << TX39_MEMCONFIG4_RFSHVAL1_SHIFT)))
|
|
|
|
#define TX39_MEMCONFIG4_RFSHVAL0_SHIFT 0
|
|
#define TX39_MEMCONFIG4_RFSHVAL0_MASK 0x3f
|
|
#define TX39_MEMCONFIG4_RFSHVAL0(cr) \
|
|
(((cr) >> TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \
|
|
TX39_MEMCONFIG4_RFSHVAL0_MASK)
|
|
#define TX39_MEMCONFIG4_RFSHVAL0_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG4_RFSHVAL0_SHIFT) & \
|
|
(TX39_MEMCONFIG4_RFSHVAL0_MASK << TX39_MEMCONFIG4_RFSHVAL0_SHIFT)))
|
|
|
|
/*
|
|
* Memory Configuration 5 Register
|
|
*/
|
|
/* Address remap region 2 */
|
|
#define TX39_MEMCONFIG5_STARTVAL2_SHIFT 9
|
|
#define TX39_MEMCONFIG5_STARTVAL2_MASK 0x007fffff
|
|
#define TX39_MEMCONFIG5_STARTVAL2(cr) \
|
|
(((cr) >> TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \
|
|
TX39_MEMCONFIG5_STARTVAL2_MASK)
|
|
#define TX39_MEMCONFIG5_STARTVAL2_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG5_STARTVAL2_SHIFT) & \
|
|
(TX39_MEMCONFIG5_STARTVAL2_MASK << TX39_MEMCONFIG5_STARTVAL2_SHIFT)))
|
|
|
|
#define TX39_MEMCONFIG5_MASK2_SHIFT 0
|
|
#define TX39_MEMCONFIG5_MASK2_MASK 0xf
|
|
#define TX39_MEMCONFIG5_MASK2(cr) \
|
|
(((cr) >> TX39_MEMCONFIG5_MASK2_SHIFT) & \
|
|
TX39_MEMCONFIG5_MASK2_MASK)
|
|
#define TX39_MEMCONFIG5_MASK2_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG5_MASK2_SHIFT) & \
|
|
(TX39_MEMCONFIG5_MASK2_MASK << TX39_MEMCONFIG5_MASK2_SHIFT)))
|
|
|
|
/*
|
|
* Memory Configuration 6 Register
|
|
*/
|
|
/* Address remap region 1 */
|
|
#define TX39_MEMCONFIG6_STARTVAL1_SHIFT 9
|
|
#define TX39_MEMCONFIG6_STARTVAL1_MASK 0x007fffff
|
|
#define TX39_MEMCONFIG6_STARTVAL1(cr) \
|
|
(((cr) >> TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \
|
|
TX39_MEMCONFIG6_STARTVAL1_MASK)
|
|
#define TX39_MEMCONFIG6_STARTVAL1_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG6_STARTVAL1_SHIFT) & \
|
|
(TX39_MEMCONFIG6_STARTVAL1_MASK << TX39_MEMCONFIG6_STARTVAL1_SHIFT)))
|
|
|
|
#define TX39_MEMCONFIG6_MASK1_SHIFT 0
|
|
#define TX39_MEMCONFIG6_MASK1_MASK 0xf
|
|
#define TX39_MEMCONFIG6_MASK1(cr) \
|
|
(((cr) >> TX39_MEMCONFIG6_MASK1_SHIFT) & \
|
|
TX39_MEMCONFIG6_MASK1_MASK)
|
|
#define TX39_MEMCONFIG6_MASK1_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG6_MASK1_SHIFT) & \
|
|
(TX39_MEMCONFIG6_MASK1_MASK << TX39_MEMCONFIG6_MASK1_SHIFT)))
|
|
|
|
/*
|
|
* Memory Configuration 7 Register
|
|
*/
|
|
/* Address remap region 2 */
|
|
#define TX39_MEMCONFIG7_RMAPADD2_SHIFT 9
|
|
#define TX39_MEMCONFIG7_RMAPADD2_MASK 0x007fffff
|
|
#define TX39_MEMCONFIG7_RMAPADD2(cr) \
|
|
(((cr) >> TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \
|
|
TX39_MEMCONFIG7_RMAPADD2_MASK)
|
|
#define TX39_MEMCONFIG7_RMAPADD2_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG7_RMAPADD2_SHIFT) & \
|
|
(TX39_MEMCONFIG7_RMAPADD2_MASK << TX39_MEMCONFIG7_RMAPADD2_SHIFT)))
|
|
|
|
/*
|
|
* Memory Configuration 8 Register
|
|
*/
|
|
/* Address remap region 1 */
|
|
#define TX39_MEMCONFIG8_RMAPADD1_SHIFT 9
|
|
#define TX39_MEMCONFIG8_RMAPADD1_MASK 0x007fffff
|
|
#define TX39_MEMCONFIG8_RMAPADD1(cr) \
|
|
(((cr) >> TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \
|
|
TX39_MEMCONFIG8_RMAPADD1_MASK)
|
|
#define TX39_MEMCONFIG8_RMAPADD1_SET(cr, val) \
|
|
((cr) | (((val) << TX39_MEMCONFIG8_RMAPADD1_SHIFT) & \
|
|
(TX39_MEMCONFIG8_RMAPADD1_MASK << TX39_MEMCONFIG8_RMAPADD1_SHIFT)))
|