83 lines
2.7 KiB
ArmAsm
83 lines
2.7 KiB
ArmAsm
/* $NetBSD: udivsi3.S,v 1.3 2003/08/07 16:32:19 agc Exp $ */
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/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)udivsi3.s 5.1 (Berkeley) 5/15/90
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*/
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#include <machine/asm.h>
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#if defined(LIBC_SCCS)
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RCSID("$NetBSD: udivsi3.S,v 1.3 2003/08/07 16:32:19 agc Exp $")
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#endif
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/* r0 <= r4 / r5 */
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ENTRY(__udivsi3)
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tst r5, r5
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bt div_by_zero
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mov #0, r0
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div0u
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#define DIVSTEP rotcl r4; div1 r5, r0
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/* repeat 32 times */
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DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
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DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
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DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
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DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP; DIVSTEP;
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#undef DIVSTEP
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rotcl r4
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rts
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mov r4, r0 /* delay slot */
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div_by_zero:
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#if defined(_KERNEL) || defined(_STANDALONE)
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rts
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mov #0, r0 /* delay slot */
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#else
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mov.l r14, @-r15
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sts.l pr, @-r15
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mov r15, r14
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mov.l L_raise, r1
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jsr @r1
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mov #8, r4 /* delay slot */
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mov #0, r0
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lds.l @r15+, pr
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rts
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mov.l @r15+, r14 /* delay slot */
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.align 2
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L_raise:
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.long _raise
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#endif
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