89 lines
4.2 KiB
C
89 lines
4.2 KiB
C
/* $NetBSD: dmphyreg.h,v 1.1 2000/02/02 04:29:49 thorpej Exp $ */
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/*-
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* Copyright (c) 2000 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _DEV_MII_DMPHYREG_H_
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#define _DEV_MII_DMPHYREG_H_
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/*
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* Davicom DM9101 registers.
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*/
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#define MII_DMPHY_DSCR 0x10 /* DAVICOM Specified Config Reg */
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#define DSCR_BP_4B5B 0x8000 /* bypass 4b5b encoding/decoding */
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#define DSCR_SCR 0x4000 /* bypass scrambler/descrambler */
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#define DSCR_ALIGN 0x2000 /* bypass symbol alignment */
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#define DSCR_REPEATER 0x0800 /* repeater mode */
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#define DSCR_TX 0x0400 /* 1 == 100baseTX, 0 == 100baseFX */
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#define DSCR_UTP 0x0200 /* 1 == UTP, 0 == STP */
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#define DSCR_CLK25MDIS 0x0100 /* CLK25M disable */
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#define DSCR_F_LINK_100 0x0080 /* force good link in 100Mb/s mode */
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#define DSCR_LINKLED_CTL 0x0020 /* 1 == link only, 0 == link+traffic */
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#define DSCR_FDXLEN_MODE 0x0010 /* 1 == 10baseT polarity, 0 == FDX */
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#define DSCR_SMRST 0x0008 /* reset state machine */
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#define DSCR_MFPSC 0x0004 /* MF preamble suppression */
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#define DSCR_SLEEP 0x0002 /* sleep mode */
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#define DSCR_RLOUT 0x0001 /* remote loop-out control */
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#define MII_DMPHY_DSCSR 0x11 /* DAVICOM Spec'd Conf/Stat Reg */
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#define DSCSR_100FDX 0x8000 /* 100Mb/s FDX */
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#define DSCSR_100HDX 0x4000 /* 100Mb/s HDX */
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#define DSCSR_10FDX 0x2000 /* 10Mb/s FDX */
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#define DSCSR_10HDX 0x1000 /* 10Mb/s HDX */
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#define DSCSR_PHYAD 0x01f0 /* PHY address */
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#define DSCSR_ANMB 0x000f /* Autonegotiation monitor */
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#define ANMB_IDLE 0x0000 /* idle */
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#define ANMB_AB_MATCH 0x0001 /* ability match */
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#define ANMB_ACK_MATCH 0x0002 /* acknowledge match */
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#define ANMB_ACK_MATCH_FAIL 0x0003 /* acknowledge match fail */
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#define ANMB_CON_MATCH 0x0004 /* consistency match */
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#define ANMB_CON_MATCH_FAIL 0x0005 /* consistency match fail */
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#define ANMB_PAR_LINK 0x0006 /* par detect signal link ready */
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#define ANMB_PAR_LINK_FAIL 0x0007 /* par detect signal link ready fail */
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#define ANMB_ANEG_OK 0x0008 /* autonegotiation completed ok */
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#define MII_DMPHY_BTCSR 0x12 /* 10baseT Configuration/Status */
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#define BTCSR_LP_EN 0x4000 /* link pulse enable */
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#define BTCSR_HBE 0x2000 /* heartbeat enable */
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#define BTCSR_JABEN 0x0800 /* jabber enable */
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#define BTCSR_10BT_SER 0x0400 /* 10baseT serial mode */
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#define BTCSR_POLR 0x0001 /* polarity reversed */
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#endif /* _DEV_MII_DMPHYREG_H_ */
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