273 lines
6.6 KiB
ArmAsm
273 lines
6.6 KiB
ArmAsm
/*-
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* Copyright (c) 2015 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "opt_com.h"
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#include "opt_cpuoptions.h"
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#include "opt_cputypes.h"
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#include "opt_multiprocessor.h"
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#include "opt_arm_debug.h"
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#include <arm/asm.h>
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#include <arm/armreg.h>
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#include "assym.h"
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RCSID("$NetBSD: rpi2_start.S,v 1.3 2015/12/17 08:02:42 skrll Exp $")
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#if defined(VERBOSE_INIT_ARM)
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#define XPUTC(n) mov r0, n; bl plputc
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#if KERNEL_BASE_VOFFSET == 0
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#define XPUTC2(n) mov r0, n; bl plputc
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#else
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#define XPUTC2(n) mov r0, n; blx r11
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#endif
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#ifdef __ARMEB__
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#define COM_BSWAP
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#endif
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#define COM_MULT 4
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#else
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#define XPUTC(n)
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#define XPUTC2(n)
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#endif
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#define INIT_MEMSIZE 128
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#define TEMP_L1_TABLE (KERNEL_BASE - KERNEL_BASE_VOFFSET + INIT_MEMSIZE * L1_S_SIZE - L1_TABLE_SIZE)
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#define MD_CPU_HATCH _C_LABEL(bcm2836_cpu_hatch)
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/*
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* Kernel start routine for RPI2 board.
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* At this point, this code has been loaded into SDRAM
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* and the MMU maybe on or maybe off.
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*/
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#ifdef KERNEL_BASES_EQUAL
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.text
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#else
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.section .start,"ax",%progbits
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#endif
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.global _C_LABEL(rpi_start)
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_C_LABEL(rpi_start):
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#ifdef __ARMEB__
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setend be /* force big endian */
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#endif
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/*
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* Save any arguments passed to us.
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*/
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movw r4, #:lower16:rpi_boot_regs
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movt r4, #:upper16:rpi_boot_regs
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#if KERNEL_BASE_VOFFSET != 0
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/*
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* But since .start is at 0x40000000 and .text is at 0x8000000, we
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* can't directly use the address that the linker gave us directly.
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* We have to adjust the address the linker gave us to get the to
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* the physical address.
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*/
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sub r4, r4, #KERNEL_BASE_VOFFSET
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#endif
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stmia r4, {r0-r3} // Save the arguments
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/*
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* Setup the CPU
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*/
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bl cortex_init
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/*
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* Set up a preliminary mapping in the MMU to allow us to run
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* at KERNEL_BASE with caches on.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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movw r1, #:lower16:.Lmmu_init_table
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movt r1, #:upper16:.Lmmu_init_table
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#if !defined(KERNEL_BASES_EQUAL)
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sub r8, r8, #KERNEL_BASE_VOFFSET
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#endif
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bl arm_boot_l1pt_init
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XPUTC(#'D')
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/*
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* Turn on the MMU, Caches, etc. Return to new enabled address space.
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*/
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movw r0, #:lower16:TEMP_L1_TABLE
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movt r0, #:upper16:TEMP_L1_TABLE
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#if KERNEL_BASE_VOFFSET == 0
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bl arm_cpuinit
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#else
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/*
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* After the MMU is on, we can execute in the normal .text segment
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* so setup the lr to be in .text. Cache the address for plputc
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* before we go.
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*/
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#if defined(VERBOSE_INIT_ARM)
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adr r11, plputc @ for XPUTC2
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#endif
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movw lr, #:lower16:1f
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movt lr, #:upper16:1f
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b arm_cpuinit
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.pushsection .text,"ax",%progbits
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1:
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#endif
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XPUTC2(#'Z')
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#if defined(MULTIPROCESSOR)
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// Now spin up the second processors into the same state we are now.
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XPUTC2(#'M')
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XPUTC2(#'P') // 'P'
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XPUTC2(#'<') // '<'
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// Make sure the cache is flushed out to RAM for the other CPUs
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bl _C_LABEL(armv7_dcache_wbinv_all)
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XPUTC2(#'>') // '>'
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#endif /* MULTIPROCESSOR */
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XPUTC2(#13)
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XPUTC2(#10)
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/*
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* Jump to start in locore.S, which in turn will call initarm and main.
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*/
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b start
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/* NOTREACHED */
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#ifndef KERNEL_BASES_EQUAL
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.popsection
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#endif
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#include <arm/cortex/a9_mpsubr.S>
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#if defined(VERBOSE_INIT_ARM)
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#define PL01XCOM_FR 0x18 /* Flag Register */
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#define PL01XCOM_DR 0x00 /* Data Register */
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#define PL01X_FR_TXFE 0x080 /* Transmit fifo empty */
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#define COM_DATA PL01XCOM_DR
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#define COM_LSR PL01XCOM_FR
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#define LSR_TSRE PL01X_FR_TXFE
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#define COM_MULT 4
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#define CONSADDR 0x3f201000
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#define TIMO 0x25000
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#ifndef COM_MULT
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#define COM_MULT 1
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#endif
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.global _C_LABEL(plputc)
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_C_LABEL(plputc):
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mov r2, #TIMO
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movw r3, #:lower16:CONSADDR
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movt r3, #:upper16:CONSADDR
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1:
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#if COM_MULT == 1
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ldrb r1, [r3, #(COM_LSR*COM_MULT)]
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#else
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#if COM_MULT == 2
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ldrh r1, [r3, #(COM_LSR*COM_MULT)]
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#elif COM_MULT == 4
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ldr r1, [r3, #(COM_LSR*COM_MULT)]
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#endif
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#ifdef COM_BSWAP
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lsr r1, r1, #(COM_MULT-1)*8
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#endif
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#endif
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tst r1, #LSR_TSRE
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bne 2f
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subs r2, r2, #1
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bne 1b
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2:
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#if COM_MULT == 1
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strb r0, [r3, #COM_DATA]
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#else
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#ifdef COM_BSWAP
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lsl r0, r0, #(COM_MULT-1)*8
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#endif
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#if COM_MULT == 2
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strh r0, [r3, #COM_DATA]
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#else
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str r0, [r3, #COM_DATA]
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#endif
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#endif
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mov r2, #TIMO
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3:
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#if COM_MULT == 1
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ldrb r1, [r3, #(COM_LSR*COM_MULT)]
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#else
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#if COM_MULT == 2
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ldrh r1, [r3, #(COM_LSR*COM_MULT)]
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#elif COM_MULT == 4
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ldr r1, [r3, #(COM_LSR*COM_MULT)]
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#endif
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#ifdef COM_BSWAP
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lsr r1, r1, #(COM_MULT-1)*8
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#endif
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#endif
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tst r1, #LSR_TSRE
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bne 4f
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subs r2, r2, #1
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bne 3b
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4:
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bx lr
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#endif /* VERBOSE_INIT_ARM */
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.Lmmu_init_table:
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/* Map KERNEL_BASE VA to SDRAM PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE, KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#if KERNEL_BASE_VOFFSET != 0
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/* Map memory 1:1 VA to PA, write-back cacheable, shareable */
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MMU_INIT(KERNEL_BASE - KERNEL_BASE_VOFFSET,
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KERNEL_BASE - KERNEL_BASE_VOFFSET, INIT_MEMSIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_CACHEABLE)
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#endif
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/* Map the 16MB of peripherals */
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MMU_INIT(RPI_KERNEL_IO_VBASE, RPI_KERNEL_IO_PBASE,
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(RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* Map the 16MB of peripherals */
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MMU_INIT(RPI_KERNEL_IO_PBASE, RPI_KERNEL_IO_PBASE,
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(RPI_KERNEL_IO_VSIZE + L1_S_SIZE - 1) / L1_S_SIZE,
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L1_S_PROTO_armv7 | L1_S_APv7_KRW | L1_S_V6_XN)
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/* end of table */
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MMU_INIT(0, 0, 0, 0)
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END(_C_LABEL(rpi_start))
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