244 lines
6.6 KiB
C
244 lines
6.6 KiB
C
/* $NetBSD: s3c2800_intr.c,v 1.9 2005/12/24 20:06:52 perry Exp $ */
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/*
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* Copyright (c) 2002 Fujitsu Component Limited
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* Copyright (c) 2002 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* IRQ handler for Samsung S3C2800 processor.
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* It has integrated interrupt controller.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: s3c2800_intr.c,v 1.9 2005/12/24 20:06:52 perry Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <uvm/uvm_extern.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include <arm/s3c2xx0/s3c2800reg.h>
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#include <arm/s3c2xx0/s3c2800var.h>
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/*
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* interrupt dispatch table.
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*/
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struct s3c2xx0_intr_dispatch handler[ICU_LEN];
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volatile int softint_pending;
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volatile int current_spl_level;
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volatile int intr_mask; /* XXX: does this need to be volatile? */
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volatile int global_intr_mask = 0; /* mask some interrupts at all spl level */
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/* interrupt masks for each level */
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int s3c2xx0_imask[NIPL];
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int s3c2xx0_ilevel[ICU_LEN];
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vaddr_t intctl_base; /* interrupt controller registers */
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#define icreg(offset) \
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(*(volatile uint32_t *)(intctl_base+(offset)))
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/*
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* Map a software interrupt queue to an interrupt priority level.
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*/
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static const int si_to_ipl[SI_NQUEUES] = {
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IPL_SOFT, /* SI_SOFT */
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IPL_SOFTCLOCK, /* SI_SOFTCLOCK */
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IPL_SOFTNET, /* SI_SOFTNET */
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IPL_SOFTSERIAL, /* SI_SOFTSERIAL */
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};
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/*
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* Clearing interrupt pending bits affects some built-in
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* peripherals. For example, IIC starts transmitting next data when
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* its interrupt pending bit is cleared.
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* We need to leave those bits to peripheral handlers.
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*/
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#define PENDING_CLEAR_MASK (~((1<<S3C2800_INT_IIC0)|(1<<S3C2800_INT_IIC1)))
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/*
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* called from irq_entry.
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*/
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void s3c2800_irq_handler(struct clockframe *);
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void
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s3c2800_irq_handler(struct clockframe *frame)
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{
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uint32_t irqbits;
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int irqno;
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int saved_spl_level;
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saved_spl_level = current_spl_level;
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while ((irqbits = icreg(INTCTL_IRQPND) & ICU_INT_HWMASK) != 0) {
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for (irqno = ICU_LEN-1; irqno >= 0; --irqno)
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if (irqbits & (1<<irqno))
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break;
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if (irqno < 0)
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break;
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/* raise spl to stop interrupts of lower priorities */
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if (saved_spl_level < handler[irqno].level)
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s3c2xx0_setipl(handler[irqno].level);
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/* clear pending bit */
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icreg(INTCTL_SRCPND) = PENDING_CLEAR_MASK & (1 << irqno);
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enable_interrupts(I32_bit); /* allow nested interrupts */
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(*handler[irqno].func) (
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handler[irqno].cookie == 0
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? frame : handler[irqno].cookie);
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disable_interrupts(I32_bit);
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/* restore spl to that was when this interrupt happen */
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s3c2xx0_setipl(saved_spl_level);
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}
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if (softint_pending & intr_mask)
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s3c2xx0_do_pending(1);
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}
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static const u_char s3c2800_ist[] = {
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EXTINTR_LOW, /* NONE */
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EXTINTR_FALLING, /* PULSE */
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EXTINTR_FALLING, /* EDGE */
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EXTINTR_LOW, /* LEVEL */
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EXTINTR_HIGH,
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EXTINTR_RISING,
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EXTINTR_BOTH,
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};
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void *
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s3c2800_intr_establish(int irqno, int level, int type,
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int (* func) (void *), void *cookie)
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{
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int save;
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if (irqno < 0 || irqno >= ICU_LEN ||
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type < IST_NONE || IST_EDGE_BOTH < type)
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panic("intr_establish: bogus irq or type");
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save = disable_interrupts(I32_bit);
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handler[irqno].cookie = cookie;
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handler[irqno].func = func;
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handler[irqno].level = level;
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s3c2xx0_update_intr_masks(irqno, level);
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if (irqno <= S3C2800_INT_EXT(7)) {
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/*
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* Update external interrupt control
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*/
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uint32_t reg;
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u_int trig;
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trig = s3c2800_ist[type];
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reg = bus_space_read_4(s3c2xx0_softc->sc_iot,
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s3c2xx0_softc->sc_gpio_ioh,
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GPIO_EXTINTR);
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reg = reg & ~(0x0f << (4*irqno));
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reg |= trig << (4*irqno);
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bus_space_write_4(s3c2xx0_softc->sc_iot, s3c2xx0_softc->sc_gpio_ioh,
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GPIO_EXTINTR, reg);
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}
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s3c2xx0_setipl(current_spl_level);
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restore_interrupts(save);
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return (&handler[irqno]);
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}
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static void
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init_interrupt_masks(void)
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{
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int i;
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s3c2xx0_imask[IPL_NONE] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK) |
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SI_TO_IRQBIT(SI_SOFT);
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s3c2xx0_imask[IPL_SOFT] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET) | SI_TO_IRQBIT(SI_SOFTCLOCK);
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/*
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* splsoftclock() is the only interface that users of the
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* generic software interrupt facility have to block their
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* soft intrs, so splsoftclock() must also block IPL_SOFT.
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*/
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s3c2xx0_imask[IPL_SOFTCLOCK] = SI_TO_IRQBIT(SI_SOFTSERIAL) |
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SI_TO_IRQBIT(SI_SOFTNET);
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/*
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* splsoftnet() must also block splsoftclock(), since we don't
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* want timer-driven network events to occur while we're
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* processing incoming packets.
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*/
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s3c2xx0_imask[IPL_SOFTNET] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (i = IPL_BIO; i < IPL_SOFTSERIAL; ++i)
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s3c2xx0_imask[i] = SI_TO_IRQBIT(SI_SOFTSERIAL);
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for (; i < NIPL; ++i)
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s3c2xx0_imask[i] = 0;
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}
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void
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s3c2800_intr_init(struct s3c2800_softc *sc)
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{
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intctl_base = (vaddr_t) bus_space_vaddr(sc->sc_sx.sc_iot,
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sc->sc_sx.sc_intctl_ioh);
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s3c2xx0_intr_mask_reg = (uint32_t *)(intctl_base + INTCTL_INTMSK);
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/* clear all pending interrupt */
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icreg(INTCTL_SRCPND) = 0xffffffff;
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init_interrupt_masks();
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s3c2xx0_intr_init(handler, ICU_LEN);
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}
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