264 lines
6.6 KiB
C
264 lines
6.6 KiB
C
/* $NetBSD: mq200machdep.c,v 1.6 2007/10/17 19:54:28 garbled Exp $ */
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/*-
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* Copyright (c) 2001 TAKEMURA Shin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#ifdef _KERNEL
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: mq200machdep.c,v 1.6 2007/10/17 19:54:28 garbled Exp $");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#else
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#include <stdio.h>
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#endif
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#include <sys/types.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include "opt_mq200.h"
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#include "mq200var.h"
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#include "mq200reg.h"
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#include "mq200priv.h"
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#if MQ200_SETUPREGS
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#define OP_(n) (((n) << 2) | 1)
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#define OP_END OP_(1)
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#define OP_MASK OP_(2)
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#define OP_LOADPLLPARAM OP_(3)
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#define OP_LOADFROMREG OP_(4)
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#define OP_STORETOREG OP_(5)
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#define OP_LOADIMM OP_(6)
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#define OP_OR OP_(7)
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static void mq200_setupregs(struct mq200_softc *sc, u_int32_t *ops);
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static u_int32_t mcr530_init_ops[] = {
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MQ200_PMCR, 0, /* power management control */
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MQ200_DCMISCR, MQ200_DCMISC_OSC_ENABLE |
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MQ200_DCMISC_FASTPOWSEQ_DISABLE |
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MQ200_DCMISC_OSCFREQ_12_25,
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OP_END
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};
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#endif /* MQ200_SETUPREGS */
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static struct mq200_clock_setting mcr530_clocks[] = {
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/* CRT: off FP: off */
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{
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MQ200_CLOCK_PLL1, /* memory clock */
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MQ200_CLOCK_PLL1, /* graphics engine clock */
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{
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0, /* GC1(CRT) clock */
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0, /* GC2(FP) clock */
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},
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30000, /* PLL1 30MHz */
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0, /* PLL2 disable */
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0, /* PLL3 disable */
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},
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/* CRT: on FP: off */
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{
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MQ200_CLOCK_PLL1, /* memory clock */
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MQ200_CLOCK_PLL2, /* graphics engine clock */
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{
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MQ200_CLOCK_PLL3, /* GC1(CRT) clock */
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0, /* GC2(FP) clock */
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},
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83000, /* PLL1 83MHz */
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30000, /* PLL2 30MHz */
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-1, /* PLL3 will be set by GC1 */
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},
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/* CRT: off FP: on */
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{
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MQ200_CLOCK_PLL1, /* memory clock */
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MQ200_CLOCK_PLL2, /* graphics engine clock */
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{
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0, /* GC1(CRT) clock */
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MQ200_CLOCK_PLL2, /* GC2(FP) clock */
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},
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30000, /* PLL1 30MHz */
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18800, /* PLL2 18.8MHz */
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0, /* PLL3 disable */
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},
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/* CRT: on FP: on */
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{
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MQ200_CLOCK_PLL1, /* memory clock */
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MQ200_CLOCK_PLL2, /* graphics engine clock */
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{
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MQ200_CLOCK_PLL3, /* GC1(CRT) clock */
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MQ200_CLOCK_PLL2, /* GC2(FP) clock */
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},
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83000, /* PLL1 83MHz */
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18800, /* PLL2 18.8MHz */
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-1, /* PLL3 will be set by GC1 */
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},
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};
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static struct mq200_md_param machdep_params[] = {
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{
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&platid_mask_MACH_NEC_MCR_530,
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640, 240, /* flat panel size */
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12288, /* base clock is 12.288 MHz */
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MQ200_MD_HAVECRT | MQ200_MD_HAVEFP,
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#if MQ200_SETUPREGS
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mcr530_init_ops,
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#else
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NULL,
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#endif /* MQ200_SETUPREGS */
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mcr530_clocks,
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/* DCMISC */
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MQ200_DCMISC_OSC_ENABLE |
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MQ200_DCMISC_FASTPOWSEQ_DISABLE |
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MQ200_DCMISC_OSCFREQ_12_25,
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/* PMC */
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0,
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/* MM01 */
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MQ200_MM01_DRAM_AUTO_REFRESH_EN |
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MQ200_MM01_GE_PB_EN |
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MQ200_MM01_CPU_PB_EN |
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MQ200_MM01_SLOW_REFRESH_EN |
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(0x143e << MQ200_MM01_REFRESH_SHIFT),
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},
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{
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&platid_mask_MACH_NEC_MCR_530A,
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640, 240, /* flat panel size */
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12288, /* base clock is 12.288 MHz */
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MQ200_MD_HAVECRT | MQ200_MD_HAVEFP,
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#if MQ200_SETUPREGS
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mcr530_init_ops,
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#else
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NULL,
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#endif /* MQ200_SETUPREGS */
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mcr530_clocks,
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/* DCMISC */
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MQ200_DCMISC_OSC_ENABLE |
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MQ200_DCMISC_FASTPOWSEQ_DISABLE |
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MQ200_DCMISC_OSCFREQ_12_25,
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/* PMC */
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0,
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/* MM01 */
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MQ200_MM01_DRAM_AUTO_REFRESH_EN |
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MQ200_MM01_GE_PB_EN |
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MQ200_MM01_CPU_PB_EN |
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MQ200_MM01_SLOW_REFRESH_EN |
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(0x143e << MQ200_MM01_REFRESH_SHIFT),
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},
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{
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NULL /* md_platform */
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}
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};
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void
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mq200_mdsetup(struct mq200_softc *sc)
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{
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const struct mq200_md_param *mdp;
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sc->sc_md = NULL;
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for (mdp = machdep_params; mdp->md_platform != NULL; mdp++) {
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platid_mask_t mask;
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mask = PLATID_DEREF(mdp->md_platform);
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if (platid_match(&platid, &mask)) {
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sc->sc_md = mdp;
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break;
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}
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}
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if (sc->sc_md) {
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sc->sc_width[MQ200_GC2] = mdp->md_fp_width;
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sc->sc_height[MQ200_GC2] = mdp->md_fp_height;
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sc->sc_baseclock = mdp->md_baseclock;
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sc->sc_regctxs[MQ200_I_DCMISC ].val = mdp->md_init_dcmisc;
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sc->sc_regctxs[MQ200_I_PMC ].val = mdp->md_init_pmc;
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sc->sc_regctxs[MQ200_I_MM01 ].val = mdp->md_init_mm01;
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#if MQ200_SETUPREGS
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mq200_setupregs(sc, mdp->md_init_ops);
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#endif
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}
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}
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#if MQ200_SETUPREGS
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static void
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mq200_setupregs(struct mq200_softc *sc, u_int32_t *ops)
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{
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u_int32_t reg, mask, accum;
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while (1) {
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switch (ops[0] & 0x3) {
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case 0:
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if (mask == ~0) {
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mq200_write(sc, ops[0], ops[1]);
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} else {
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reg = mq200_read(sc, ops[0]);
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reg = (reg & ~mask) | (ops[1] & mask);
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mq200_write(sc, ops[0], reg);
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}
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break;
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case 1:
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switch (ops[0]) {
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case OP_END:
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return;
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case OP_MASK:
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mask = ops[1];
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break;
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case OP_LOADPLLPARAM:
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mq200_pllparam(ops[1], &accum);
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break;
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case OP_LOADFROMREG:
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reg = mq200_read(sc, ops[1]);
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accum = (accum & ~mask) | (reg & mask);
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break;
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case OP_STORETOREG:
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if (mask == ~0) {
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mq200_write(sc, ops[1], accum);
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} else {
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reg = mq200_read(sc, ops[1]);
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reg = (reg & ~mask) | (accum & mask);
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mq200_write(sc, ops[1], reg);
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}
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break;
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case OP_LOADIMM:
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accum = (accum & ~mask) | (ops[1] & mask);
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break;
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case OP_OR:
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accum = (accum | ops[1]);
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break;
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}
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break;
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}
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if (ops[0] != OP_MASK)
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mask = ~0;
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ops += 2;
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}
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}
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#endif /* MQ200_SETUPREGS */
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