72 lines
2.9 KiB
C
72 lines
2.9 KiB
C
/*
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* adapted/extracted from omap_wdt.c
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*
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* Copyright (c) 2007 Microsoft
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Microsoft
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTERS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _OMAP_WDTREG_H
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#define _OMAP_WDTREG_H
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#define PTV 1 /* prescaler ratio: clock is divided by 2 */
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#define PRE 1 /* enable divided input clock */
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#define TCLK 32768 /* timer clock period in normal mode */
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#define WIDR 0x00 /* watchdog ID reg offset */
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#define WD_REV 0xff /* WIDR rev field mask */
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#define WD_SYSCONFIG 0x10 /* WD System Configuration register */
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#define WD_SYSCONFIG_AUTOIDLE 0x0 /* interface clock autogating */
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#define WCLR 0x24 /* watchdog control register */
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#define WCLR_PRE(PRE) ((PRE & 0x1)<<5)
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#define WCLR_PTV(PTV) ((PTV & 0x7)<<2)
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#define WCRR 0x28 /* watchdog counter register */
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#define WLDR 0x2c /* watchdog load register */
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#define WTGR 0x30 /* watchdog trigger register */
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#define WWPS 0x34 /* watchdog write pending register */
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#define W_PEND_WSPR (1<<4)
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#define W_PEND_WTGR (1<<3)
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#define W_PEND_WLDR (1<<2)
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#define W_PEND_WCRR (1<<1)
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#define W_PEND_WCLR (1<<0)
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#define WSPR 0x48 /* watchdog start/stop register */
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#define WD_ENABLE_WORD1 0x0000BBBB
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#define WD_ENABLE_WORD2 0x00004444
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#define WD_DISABLE_WORD1 0x0000AAAA
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#define WD_DISABLE_WORD2 0x00005555
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/* compute number of ticks corresponding to timeout seconds */
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#define WATCHDOG_COUNT(timeout) (~((timeout) * TCLK / (1<<PTV) -1))
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#endif /* _OMAP_WDTREG_H */
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