168 lines
7.3 KiB
C
168 lines
7.3 KiB
C
/* $NetBSD: omap_dmtimerreg.h,v 1.1 2012/12/11 19:01:18 riastradh Exp $ */
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/*
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* TI OMAP Dual-mode timers: Registers
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*/
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/*-
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* Copyright (c) 2012 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Taylor R. Campbell.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* References: TI AM335x TRM, TI OMAP35x TRM.
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*/
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#ifndef _ARM_OMAP_OMAP_DMTIMERREG_H_
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#define _ARM_OMAP_OMAP_DMTIMERREG_H_
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#include <sys/cdefs.h>
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#define OMAP_DMTIMER_ID 0x00 /* TIDR */
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#define OMAP_DMTIMER_OCP_CFG 0x10 /* TOCP_CFG */
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#define OMAP_DMTIMER_OCP_CFG_IDLEMODE_FORCE_IDLE 0
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#define OMAP_DMTIMER_OCP_CFG_IDLEMODE_NO_IDLE 1
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#define OMAP_DMTIMER_OCP_CFG_IDLEMODE_SMART_IDLE 2
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#define OMAP_DMTIMER_OCP_CFG_IDLEMODE_RESERVED 3
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/*
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* DM timer version 1
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*/
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#define OMAP_DMTIMER_V1_ID_REVISION_MASK __BITS(0, 7)
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#define OMAP_DMTIMER_V1_ID_RESERVED_MASK __BITS(8, 31)
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#define OMAP_DMTIMER_V1_OCP_CFG_AUTOIDLE_MASK __BITS(0, 0)
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#define OMAP_DMTIMER_V1_OCP_CFG_SOFTRESET_MASK __BITS(1, 1)
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#define OMAP_DMTIMER_V1_OCP_CFG_WAKEUP_MASK __BITS(2, 2)
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#define OMAP_DMTIMER_V1_OCP_CFG_IDLEMODE_MASK __BITS(3, 4)
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#define OMAP_DMTIMER_V1_OCP_CFG_EMUFREE_MASK __BITS(5, 5)
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#define OMAP_DMTIMER_V1_OCP_CFG_RESERVED0_MASK __BITS(6, 8)
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#define OMAP_DMTIMER_V1_OCP_CFG_CLOCKACT_MASK __BITS(9, 8)
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#define OMAP_DMTIMER_V1_OCP_CFG_CLOCKACT_OFF 0
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#define OMAP_DMTIMER_V1_OCP_CFG_CLOCKACT_FUN 1
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#define OMAP_DMTIMER_V1_OCP_CFG_CLOCKACT_L4 2
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#define OMAP_DMTIMER_V1_OCP_CFG_CLOCKACT_L4_FUN 3
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#define OMAP_DMTIMER_INTR_MATCH __BIT(0)
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#define OMAP_DMTIMER_INTR_OVERFLOW __BIT(1)
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#define OMAP_DMTIMER_INTR_CAPTURE __BIT(2)
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#define OMAP_DMTIMER_INTR_ALL 0x7
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#define OMAP_DMTIMER_V1_STATUS 0x14 /* TISTAT */
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#define OMAP_DMTIMER_V1_STATUS_RESETDONE __BIT(0)
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#define OMAP_DMTIMER_V1_INTR_STATUS 0x18 /* TISR */
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#define OMAP_DMTIMER_V1_INTR_ENABLE 0x1c /* TIER */
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#define OMAP_DMTIMER_V1_TIMER_REGS 0x20
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/*
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* DM timer version 2
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*/
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#define OMAP_DMTIMER_V2_ID_Y_MINOR_MASK __BITS(0, 5)
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#define OMAP_DMTIMER_V2_ID_CUSTOM_MASK __BITS(6, 7)
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#define OMAP_DMTIMER_V2_ID_X_MAJOR_MASK __BITS(8, 10)
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#define OMAP_DMTIMER_V2_ID_R_RTL_MASK __BITS(11, 15)
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#define OMAP_DMTIMER_V2_ID_FUNC_MASK __BITS(16, 27)
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#define OMAP_DMTIMER_V2_ID_RESERVED_MASK __BITS(28, 29)
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#define OMAP_DMTIMER_V2_ID_SCHEME_MASK __BITS(30, 31)
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#define OMAP_DMTIMER_V2_OCP_CFG_SOFTRESET_MASK __BITS(0, 0)
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#define OMAP_DMTIMER_V2_OCP_CFG_EMUFREE_MASK __BITS(1, 1)
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#define OMAP_DMTIMER_V2_OCP_CFG_IDLEMODE_MASK __BITS(2, 3)
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#define OMAP_DMTIMER_V2_INTR_STATUS_RAW 0x24
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#define OMAP_DMTIMER_V2_INTR_STATUS 0x28
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#define OMAP_DMTIMER_V2_INTR_ENABLE_SET 0x2c
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#define OMAP_DMTIMER_V2_INTR_ENABLE_CLEAR 0x30
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#define OMAP_DMTIMER_V2_TIMER_REGS 0x34
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#define OMAP_DMTIMER_REG_INDEX_MASK 0x00ff
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#define OMAP_DMTIMER_REG_POSTED_BIT_MASK 0x0f00
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#define OMAP_DMTIMER_REG_POSTED_INDEX(reg) \
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__SHIFTOUT((reg), OMAP_DMTIMER_REG_INDEX_MASK)
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#define OMAP_DMTIMER_REG_POSTED_BIT(reg) \
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__SHIFTOUT((reg), OMAP_DMTIMER_REG_POSTED_BIT_MASK)
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#define OMAP_DMTIMER_REG_POSTED_MASK(reg) \
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__BIT(OMAP_DMTIMER_REG_POSTED_BIT(reg))
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#define OMAP_DMTIMER_REG_POSTED_P(reg) \
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(((reg) & 0x1000) == 0x1000)
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#define OMAP_DMTIMER_TIMER_INTR_WAKEUP 0x0000 /* TWER */
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#define OMAP_DMTIMER_TIMER_CTRL 0x1004 /* TCLR */
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#define OMAP_DMTIMER_TIMER_CTRL_START __BIT(0)
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#define OMAP_DMTIMER_TIMER_CTRL_AUTORELOAD __BIT(1)
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#define OMAP_DMTIMER_TIMER_CTRL_PRESCALE_MASK __BITS(2, 4)
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#define OMAP_DMTIMER_TIMER_CTRL_PRESCALE_ENABLE __BIT(5)
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#define OMAP_DMTIMER_TIMER_CTRL_COMPARE_ENABLE __BIT(6)
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#define OMAP_DMTIMER_TIMER_CTRL_PWM_SIGN __BIT(7)
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#define OMAP_DMTIMER_TIMER_CTRL_TCM_MASK __BITS(8, 9)
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#define OMAP_DMTIMER_TIMER_CTRL_TCM_NONE 0
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#define OMAP_DMTIMER_TIMER_CTRL_TCM_LOW_HIGH 1
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#define OMAP_DMTIMER_TIMER_CTRL_TCM_HIGH_LOW 2
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#define OMAP_DMTIMER_TIMER_CTRL_TCM_BOTH 3
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#define OMAP_DMTIMER_TIMER_CTRL_TRG_MASK __BITS(10, 11)
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#define OMAP_DMTIMER_TIMER_CTRL_TRG_NONE 0
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#define OMAP_DMTIMER_TIMER_CTRL_TRG_OVERFLOW 1
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#define OMAP_DMTIMER_TIMER_CTRL_TRG_OVERFLOW_MATCH 2
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#define OMAP_DMTIMER_TIMER_CTRL_TRG_RESERVED 3
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#define OMAP_DMTIMER_TIMER_CTRL_PWM_PT __BIT(12)
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#define OMAP_DMTIMER_TIMER_CTRL_PWM_PULSE 0
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#define OMAP_DMTIMER_TIMER_CTRL_PWM_TOGGLE 1
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#define OMAP_DMTIMER_TIMER_CTRL_CAPTURE_MODE __BIT(13)
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#define OMAP_DMTIMER_TIMER_CTRL_CAPTURE_MODE_FIRST 0
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#define OMAP_DMTIMER_TIMER_CTRL_CAPTURE_MODE_SECOND 1
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#define OMAP_DMTIMER_TIMER_CTRL_GPO_CFG __BIT(14)
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#define OMAP_DMTIMER_TIMER_COUNTER 0x1108 /* TCRR */
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#define OMAP_DMTIMER_TIMER_LOAD 0x120c /* TLDR */
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#define OMAP_DMTIMER_TIMER_TRIGGER 0x1310 /* TTGR */
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#define OMAP_DMTIMER_TIMER_WRITE_POST 0x0014 /* TWPS */
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#define OMAP_DMTIMER_TIMER_WRITE_POST_CTRL __BIT(0)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_COUNTER __BIT(1)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_LOAD __BIT(2)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_TRIGGER __BIT(3)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_MATCH __BIT(4)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_POS_INCR __BIT(5)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_NEG_INCR __BIT(6)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_COUNTER_VALUE __BIT(7)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_INTR_MASK_SET __BIT(8)
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#define OMAP_DMTIMER_TIMER_WRITE_POST_INTR_MASK_COUNT __BIT(9)
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#define OMAP_DMTIMER_TIMER_MATCH 0x1418 /* TMAR */
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#define OMAP_DMTIMER_TIMER_CAPTURE1 0x001c /* TCAR1 */
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#define OMAP_DMTIMER_TIMER_SYNC_INT_CTRL 0x0020 /* TSICR */
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#define OMAP_DMTIMER_TIMER_SYNC_INT_CTRL_SOFTRESET __BIT(1)
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#define OMAP_DMTIMER_TIMER_SYNC_INT_CTRL_POSTED __BIT(2)
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#define OMAP_DMTIMER_TIMER_CAPTURE2 0x0024 /* TCAR2 */
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#define OMAP_DMTIMER_TICK_POS_INCR 0x1528 /* TPIR */
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#define OMAP_DMTIMER_TICK_NEG_INCR 0x162c /* TNIR */
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#define OMAP_DMTIMER_TICK_COUNTER_VALUE 0x1730 /* TCVR */
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#define OMAP_DMTIMER_TICK_INTR_MASK_SET 0x1834 /* TOCR */
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#define OMAP_DMTIMER_TICK_INTR_MASK_COUNT 0x1938 /* TOWR */
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#endif /* _ARM_OMAP_OMAP_DMTIMERREG_H_ */
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