119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
/* $NetBSD: ixp12x0_clkreg.h,v 1.4 2009/10/21 14:15:50 rmind Exp $ */
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/*
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* Copyright (c) 2002
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* Ichiro FUKUHARA <ichiro@ichiro.org>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS
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* HEAD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* IXP12X0 TIMER registers
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* TIMER_1 v0xf0010300 p0x42000300
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* TIMER_2 v0xf0010320 p0x42000320
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* TIMER_3 v0xf0010340 p0x42000340
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* TIMER_4 v0xf0010360 p0x42000360
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*/
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#ifndef _IXP12X0_CLKREG_H_
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#define _IXP12X0_CLKREG_H_
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#include <arm/ixp12x0/ixp12x0reg.h>
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#define IXPCLK_PLL_CFG_OFFSET (0x90000c00U - 0x42000300U)
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#define IXPCLK_PLL_CFG_SIZE 0x04
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/* timer load register */
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#define IXPCLK_LOAD 0x00000000
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#define IXPCL_ITV 0x00ffffff
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/* timer value register */
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#define IXPCLK_VALUE 0x00000004
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#define IXPCL_CTV 0x00ffffff
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/* timer control register */
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#define IXPCLK_CONTROL 0x00000008
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#define IXPCL_STP 0x0c
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#define IXPCL_STP_CORE 0x00
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#define IXPCL_STP_DIV16 0x04
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#define IXPCL_STP_DIV256 0x08
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#define IXPCL_MODE 0x40
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#define IXPCL_FREERUN 0x00
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#define IXPCL_PERIODIC 0x40
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#define IXPCL_EN 0x80
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#define IXPCL_DISABLE 0x00
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#define IXPCL_ENABLE 0x80
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/* timer clear register */
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#define IXPCLK_CLEAR 0x0000000c
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#define IXPT_CLEAR 0
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/*
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* IXP12X0 real time clock registers
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* RTC_DIV 0x90002000
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* RTC_TINT 0x90002400
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* RTC_TVAL 0x90002800
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* RTC_CNTR 0x90002c00
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* RTC_ALM 0x90003000
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*/
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/* RTC_DIV register */
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#define RTC_DIV 0x90002000
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#define RTC_RDIV 0x0000ffff
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#define RTC_WEN 0x00010000
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#define RTC_WDIVISER 0x00000000
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#define RTC_WINTONLY 0x00010000
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#define RTC_IEN 0x00020000
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#define RTC_IEN_E 0x00020000
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#define RTC_IEN_D 0x00000000
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#define RTC_IRST 0x00040000
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#define RTC_IRST_NOCLR 0x00040000
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#define RTC_IRST_CLR 0x00000000
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#define RTC_IRQS 0x00080000
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#define RTC_IRQS_IRQ 0x00080000
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#define RTC_IRQS_FIQ 0x00000000
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/* RTC_TINT register */
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#define RTC_TINT 0x90002400
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#define RTC_RTINT 0x0000ffff
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/* RTC_TVAL register */
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#define RTC_TVAL 0x90002800
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#define RTC_TVAL_TVAL 0x0000ffff
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#define RTC_LD 0x00010000
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#define RTC_LD_LOAD 0x00010000
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#define RTC_LD_NOLOAD 0x00000000
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#define RTC_PRE 0x00020000
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#define RTC_PRE_SYSCLK 0x00020000
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#define RTC_PRE_DIV128 0x00000000
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/* RTC_CNTR register */
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#define RTC_CNTR 0x90002c00
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#define RTC_RCN_COUNT 0xffffffff
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/* RTC_ALM register */
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#define RTC_ALM 0x90003000
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#define RTC_RTC_ALARM 0xffffffff
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#endif /* _IXP12X0_CLKREG_H_ */
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