270 lines
8.3 KiB
C
270 lines
8.3 KiB
C
/* $NetBSD: awin_otg.c,v 1.5 2014/10/16 00:02:47 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: awin_otg.c,v 1.5 2014/10/16 00:02:47 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <sys/pool.h>
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#include <sys/kmem.h>
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#include <arm/allwinner/awin_reg.h>
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#include <arm/allwinner/awin_otgreg.h>
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#include <arm/allwinner/awin_var.h>
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#include <dev/usb/usb.h>
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#include <dev/usb/usbdi.h>
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#include <dev/usb/usbdivar.h>
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#include <dev/usb/usb_mem.h>
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#include <dev/usb/motgvar.h>
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struct awin_otg_softc {
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struct motg_softc sc_motg;
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void *sc_ih;
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struct awin_gpio_pindata sc_drv_pin;
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struct awin_gpio_pindata sc_restrict_pin;
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};
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#define OTG_READ1(sc, reg) \
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bus_space_read_1((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg))
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#define OTG_WRITE1(sc, reg, val) \
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bus_space_write_1((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg), (val))
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#define OTG_READ2(sc, reg) \
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bus_space_read_2((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg))
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#define OTG_WRITE2(sc, reg, val) \
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bus_space_write_2((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg), (val))
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#define OTG_READ4(sc, reg) \
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bus_space_read_4((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg))
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#define OTG_WRITE4(sc, reg, val) \
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bus_space_write_4((sc)->sc_motg.sc_iot, (sc)->sc_motg.sc_ioh, (reg), (val))
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static int awin_otg_match(device_t, cfdata_t, void *);
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static void awin_otg_attach(device_t, device_t, void *);
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static void awin_otg_init(struct awin_otg_softc *);
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static void awin_otg_phy_write(struct awin_otg_softc *, u_int,
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u_int, u_int);
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static int awin_otg_intr(void *);
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static void awin_otg_poll(void *);
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CFATTACH_DECL_NEW(awin_otg, sizeof(struct awin_otg_softc),
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awin_otg_match, awin_otg_attach, NULL, NULL);
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static int
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awin_otg_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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if (strcmp(cf->cf_name, loc->loc_name))
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return 0;
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return 1;
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}
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static void
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awin_otg_attach(device_t parent, device_t self, void *aux)
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{
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struct awin_otg_softc *sc = device_private(self);
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struct awinio_attach_args * const aio = aux;
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const struct awin_locators * const loc = &aio->aio_loc;
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aprint_naive("\n");
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aprint_normal(": OTG\n");
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if (awin_chip_id() == AWIN_CHIP_ID_A31) {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_USB_CLK_REG,
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AWIN_A31_USB_CLK_USBPHY0_ENABLE |
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AWIN_A31_USB_CLK_PHY0_ENABLE, 0);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING0_REG, AWIN_A31_AHB_GATING0_USB0, 0);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_A31_AHB_RESET0_REG, AWIN_A31_AHB_RESET0_USBOTG_RST, 0);
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} else {
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_USB0, 0);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_USB_CLK_REG,
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AWIN_USB_CLK_USBPHY_ENABLE|AWIN_USB_CLK_PHY0_ENABLE, 0);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_core_bsh,
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AWIN_SRAM_OFFSET + AWIN_SRAM_CTL1_REG,
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__SHIFTIN(AWIN_SRAM_CTL1_SRAMD_MAP_USB0,
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AWIN_SRAM_CTL1_SRAMD_MAP),
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0);
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}
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sc->sc_motg.sc_dev = self;
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sc->sc_motg.sc_bus.dmatag = aio->aio_dmat;
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sc->sc_motg.sc_iot = aio->aio_core_bst;
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bus_space_subregion(sc->sc_motg.sc_iot, aio->aio_core_bsh,
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loc->loc_offset, loc->loc_size, &sc->sc_motg.sc_ioh);
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sc->sc_motg.sc_size = loc->loc_size;
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sc->sc_motg.sc_intr_poll = awin_otg_poll;
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sc->sc_motg.sc_intr_poll_arg = sc;
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sc->sc_motg.sc_mode = MOTG_MODE_HOST;
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sc->sc_motg.sc_ep_max = 5;
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sc->sc_motg.sc_ep_fifosize = 512;
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sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
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awin_otg_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(self, "couldn't establish interrupt %d\n",
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loc->loc_intr);
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return;
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}
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device_printf(self, "interrupting at irq %d\n", loc->loc_intr);
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awin_otg_init(sc);
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motg_init(&sc->sc_motg);
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}
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static void
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awin_otg_init(struct awin_otg_softc *sc)
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{
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uint32_t val;
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/* initialize the USB phy */
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awin_otg_phy_write(sc, 0x0c, 0x01, 1);
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awin_otg_phy_write(sc, 0x20, 0x14, 5);
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awin_otg_phy_write(sc, 0x2a, 0x03, 2);
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if (awin_gpio_pin_reserve("usb0drv", &sc->sc_drv_pin)) {
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awin_gpio_pindata_write(&sc->sc_drv_pin, 1);
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} else {
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aprint_error_dev(sc->sc_motg.sc_dev, "no power gpio found\n");
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}
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if (awin_gpio_pin_reserve("usb0restrict", &sc->sc_restrict_pin)) {
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awin_gpio_pindata_write(&sc->sc_restrict_pin, 1);
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} else {
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aprint_error_dev(sc->sc_motg.sc_dev, "no restrict gpio found\n");
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}
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val = OTG_READ4(sc, AWIN_USB0_PHY_CSR_REG);
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val &= ~AWIN_USB0_PHY_CSR_VBUS_CHANGE_DET;
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val &= ~AWIN_USB0_PHY_CSR_ID_CHANGE_DET;
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val &= ~AWIN_USB0_PHY_CSR_DPDM_CHANGE_DET;
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val |= AWIN_USB0_PHY_CSR_DPDM_PULLUP_EN;
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val |= AWIN_USB0_PHY_CSR_ID_PULLUP_EN;
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val &= ~AWIN_USB0_PHY_CSR_FORCE_ID;
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val |= __SHIFTIN(AWIN_USB0_PHY_CSR_FORCE_ID_LOW,
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AWIN_USB0_PHY_CSR_FORCE_ID);
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val &= ~AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID;
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val |= __SHIFTIN(AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID_HIGH,
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AWIN_USB0_PHY_CSR_FORCE_VBUS_VALID);
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OTG_WRITE4(sc, AWIN_USB0_PHY_CSR_REG, val);
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OTG_WRITE1(sc, MUSB2_REG_AWIN_VEND0, 0);
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}
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static int
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awin_otg_intr(void *priv)
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{
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struct awin_otg_softc *sc = priv;
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uint8_t intusb;
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uint16_t inttx, intrx;
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mutex_enter(&sc->sc_motg.sc_intr_lock);
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intusb = OTG_READ1(sc, MUSB2_REG_INTUSB);
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inttx = OTG_READ2(sc, MUSB2_REG_INTTX);
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intrx = OTG_READ2(sc, MUSB2_REG_INTRX);
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if (!intusb && !inttx && !intrx) {
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mutex_exit(&sc->sc_motg.sc_intr_lock);
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return 0;
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}
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#if 0
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device_printf(sc->sc_motg.sc_dev, "ctrl %02x tx %04x rx %04x\n",
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intusb, inttx, intrx);
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#endif
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if (intusb)
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OTG_WRITE1(sc, MUSB2_REG_INTUSB, intusb);
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if (inttx)
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OTG_WRITE2(sc, MUSB2_REG_INTTX, inttx);
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if (intrx)
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OTG_WRITE2(sc, MUSB2_REG_INTRX, intrx);
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motg_intr(&sc->sc_motg, intrx, inttx, intusb);
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mutex_exit(&sc->sc_motg.sc_intr_lock);
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return 1;
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}
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static void
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awin_otg_poll(void *priv)
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{
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awin_otg_intr(priv);
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}
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static void
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awin_otg_phy_write(struct awin_otg_softc *sc, u_int bit_addr, u_int bits,
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u_int len)
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{
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bus_space_tag_t bst = sc->sc_motg.sc_iot;
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bus_space_handle_t bsh = sc->sc_motg.sc_ioh;
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uint32_t clk = AWIN_USB0_PHY_CTL_CLK0;
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bus_size_t reg = AWIN_USB0_PHY_CTL_REG;
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uint32_t v = bus_space_read_4(bst, bsh, reg);
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KASSERT((v & AWIN_USB0_PHY_CTL_CLK0) == 0);
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KASSERT((v & AWIN_USB0_PHY_CTL_CLK1) == 0);
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KASSERT((v & AWIN_USB0_PHY_CTL_CLK2) == 0);
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v &= ~AWIN_USB0_PHY_CTL_ADDR;
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v &= ~AWIN_USB0_PHY_CTL_DAT;
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v |= __SHIFTIN(bit_addr, AWIN_USB0_PHY_CTL_ADDR);
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/*
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* Bitbang the data to the phy, bit by bit, incrementing bit address
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* as we go.
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*/
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for (; len > 0; bit_addr++, bits >>= 1, len--) {
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v |= __SHIFTIN(bits & 1, AWIN_USB0_PHY_CTL_DAT);
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bus_space_write_4(bst, bsh, reg, v);
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delay(1);
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bus_space_write_4(bst, bsh, reg, v | clk);
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delay(1);
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bus_space_write_4(bst, bsh, reg, v);
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delay(1);
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v += __LOWEST_SET_BIT(AWIN_USB0_PHY_CTL_ADDR);
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v &= ~AWIN_USB0_PHY_CTL_DAT;
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}
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}
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