258 lines
7.7 KiB
C
258 lines
7.7 KiB
C
/* $NetBSD: awin_intr.h,v 1.15 2014/12/21 17:38:47 jmcneill Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_ALLWINNER_AWIN_INTR_H_
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#define _ARM_ALLWINNER_AWIN_INTR_H_
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#include "opt_allwinner.h"
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#if defined(ALLWINNER_A80)
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#define PIC_MAXSOURCES 224
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#define PIC_MAXMAXSOURCES 256
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#else
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#define PIC_MAXSOURCES 160
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#define PIC_MAXMAXSOURCES 192
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#endif
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/*
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* The Allwinner can use a generic interrupt controller so pull in that stuff.
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*/
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#include <arm/cortex/gic_intr.h>
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#include <arm/cortex/gtmr_intr.h> /* A7/A9/A15 Timer PPIs */
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/*
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* There are for the A20 but the A10 are the same but offset by 32 less.
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*/
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#define AWIN_IRQ_UART0 33
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#define AWIN_IRQ_UART1 34
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#define AWIN_IRQ_UART2 35
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#define AWIN_IRQ_UART3 36
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#define AWIN_IRQ_IR0 37
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#define AWIN_IRQ_IR1 38
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#define AWIN_IRQ_TWI0 39
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#define AWIN_IRQ_TWI1 40
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#define AWIN_IRQ_TWI2 41
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#define AWIN_IRQ_SPI0 42
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#define AWIN_IRQ_SPI1 43
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#define AWIN_IRQ_SPI2 44
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#define AWIN_IRQ_SPDIF 45
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#define AWIN_IRQ_AC97 46
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#define AWIN_IRQ_TS 47
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#define AWIN_IRQ_IIS0 48
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#define AWIN_IRQ_UART4 49
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#define AWIN_IRQ_UART5 50
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#define AWIN_IRQ_UART6 51
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#define AWIN_IRQ_UART7 52
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#define AWIN_IRQ_KEYPAD 53
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#define AWIN_IRQ_TMR0 54
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#define AWIN_IRQ_TMR1 55
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#define AWIN_IRQ_TMR2 56 /* WatchDog */
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#define AWIN_IRQ_TMR3 57
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#define AWIN_IRQ_CAN 58
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#define AWIN_IRQ_DMA 59
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#define AWIN_IRQ_PIO 60
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#define AWIN_IRQ_TP 61
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#define AWIN_IRQ_AC 62
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#define AWIN_IRQ_LRADC 63
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#define AWIN_IRQ_SDMMC0 64
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#define AWIN_IRQ_SDMMC1 65
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#define AWIN_IRQ_SDMMC2 66
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#define AWIN_IRQ_SDMMC3 67
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#define AWIN_IRQ_MS 68
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#define AWIN_IRQ_NAND 69
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#define AWIN_IRQ_USB0 70
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#define AWIN_IRQ_USB1 71 // EHCI0
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#define AWIN_IRQ_USB2 72 // EHCI1
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#define AWIN_IRQ_SCR 73
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#define AWIN_IRQ_CSI0 74
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#define AWIN_IRQ_CSI1 75
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#define AWIN_IRQ_LCD0 76
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#define AWIN_IRQ_LCD1 77
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#define AWIN_IRQ_MP 78
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#define AWIN_IRQ_DE_XE0 79
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#define AWIN_IRQ_DE_XE1 80
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#define AWIN_IRQ_PMU 81
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#define AWIN_IRQ_SPI3 82
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#define AWIN_IRQ_TZASC 83
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#define AWIN_IRQ_PATA 84
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#define AWIN_IRQ_VE 85
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#define AWIN_IRQ_SS 86
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#define AWIN_IRQ_EMAC 87
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#define AWIN_IRQ_SATA 88
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#define AWIN_IRQ__RSVD89 89
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#define AWIN_IRQ_HDMI0 90
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#define AWIN_IRQ_TVE 91
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#define AWIN_IRQ_ACE 92
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#define AWIN_IRQ_TVD 93
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#define AWIN_IRQ_PS2_0 94
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#define AWIN_IRQ_PS2_1 95
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#define AWIN_IRQ_USB3 96 // OHCI0
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#define AWIN_IRQ_USB4 97 // OHCI1
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#define AWIN_IRQ_PERFM 98
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#define AWIN_IRQ_TMR4 99
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#define AWIN_IRQ_TMR5 100
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#define AWIN_IRQ_GPU_GP 101
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#define AWIN_IRQ_GPU_GPMMU 102
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#define AWIN_IRQ_GPU_PP0 103
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#define AWIN_IRQ_GPU_PPMMU0 104
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#define AWIN_IRQ_GPU_PMU 105
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#define AWIN_IRQ_GPU_PP1 106
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#define AWIN_IRQ_GPU_PPMMU1 107
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#define AWIN_IRQ_GPU_RSV0 108
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#define AWIN_IRQ_GPU_RSV1 109
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#define AWIN_IRQ_GPU_RSV2 110
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#define AWIN_IRQ_GPU_RSV3 111
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#define AWIN_IRQ_GPU_RSV4 112
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#define AWIN_IRQ_HSTMR0 113
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#define AWIN_IRQ_HSTMR1 114
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#define AWIN_IRQ_HSTMR2 115
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#define AWIN_IRQ_HSTMR3 116
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#define AWIN_IRQ_GMAC 117
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#define AWIN_IRQ_HDMI1 118
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#define AWIN_IRQ_IIS1 119
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#define AWIN_IRQ_TWI3 120
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#define AWIN_IRQ_TWI4 121
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#define AWIN_IRQ_IIS2 122
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/*
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* A31
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*/
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#define AWIN_A31_IRQ_UART0 32
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#define AWIN_A31_IRQ_UART1 33
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#define AWIN_A31_IRQ_UART2 34
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#define AWIN_A31_IRQ_UART3 35
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#define AWIN_A31_IRQ_UART4 36
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#define AWIN_A31_IRQ_UART5 37
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#define AWIN_A31_IRQ_TWI0 38
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#define AWIN_A31_IRQ_TWI1 39
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#define AWIN_A31_IRQ_TWI2 40
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#define AWIN_A31_IRQ_TWI3 41
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#define AWIN_A31_IRQ_AC 61
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#define AWIN_A31_IRQ_CIR 69
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#define AWIN_A31_IRQ_P2WI 71
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#define AWIN_A31_IRQ_DMA 82
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#define AWIN_A31_IRQ_SDMMC0 92
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#define AWIN_A31_IRQ_SDMMC1 93
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#define AWIN_A31_IRQ_SDMMC2 94
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#define AWIN_A31_IRQ_SDMMC3 95
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#define AWIN_A31_IRQ_USB0 103
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#define AWIN_A31_IRQ_USB1 104
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#define AWIN_A31_IRQ_USB2 105
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#define AWIN_A31_IRQ_USB3 106
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#define AWIN_A31_IRQ_USB4 108
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#define AWIN_A31_IRQ_GMAC 114
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#define AWIN_A31_IRQ_MP 115
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#define AWIN_A31_IRQ_HDMI 120
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/*
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* A80
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*/
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#define AWIN_A80_IRQ_UART0 32
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#define AWIN_A80_IRQ_UART1 33
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#define AWIN_A80_IRQ_UART2 34
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#define AWIN_A80_IRQ_UART3 35
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#define AWIN_A80_IRQ_UART4 36
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#define AWIN_A80_IRQ_UART5 37
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#define AWIN_A80_IRQ_TWI0 38
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#define AWIN_A80_IRQ_TWI1 39
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#define AWIN_A80_IRQ_TWI2 40
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#define AWIN_A80_IRQ_TWI3 41
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#define AWIN_A80_IRQ_TWI4 42
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#define AWIN_A80_IRQ_PA_EINT 43
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#define AWIN_A80_IRQ_PB_EINT 47
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#define AWIN_A80_IRQ_PE_EINT 48
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#define AWIN_A80_IRQ_PG_EINT 49
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#define AWIN_A80_IRQ_TIMER0 50
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#define AWIN_A80_IRQ_TIMER1 51
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#define AWIN_A80_IRQ_TIMER2 52
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#define AWIN_A80_IRQ_TIMER3 53
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#define AWIN_A80_IRQ_TIMER4 54
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#define AWIN_A80_IRQ_TIMER5 55
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#define AWIN_A80_IRQ_WATCHDOG 56
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#define AWIN_A80_IRQ_KEYADC 62
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#define AWIN_A80_IRQ_NMI 64
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#define AWIN_A80_IRQ_R_CIR 69
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#define AWIN_A80_IRQ_R_RSB 71
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#define AWIN_A80_IRQ_R_DAUDIO 74
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#define AWIN_A80_IRQ_DMA 82
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#define AWIN_A80_IRQ_HSTIMER0 83
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#define AWIN_A80_IRQ_HSTIMER1 84
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#define AWIN_A80_IRQ_HSTIMER2 85
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#define AWIN_A80_IRQ_HSTIMER3 86
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#define AWIN_A80_IRQ_HSTIMER4 87
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#define AWIN_A80_IRQ_SMC 88
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#define AWIN_A80_IRQ_VE 90
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#define AWIN_A80_IRQ_SDMMC0 92
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#define AWIN_A80_IRQ_SDMMC1 93
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#define AWIN_A80_IRQ_SDMMC2 94
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#define AWIN_A80_IRQ_SDMMC3 95
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#define AWIN_A80_IRQ_SPI0 97
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#define AWIN_A80_IRQ_SPI1 98
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#define AWIN_A80_IRQ_SPI2 99
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#define AWIN_A80_IRQ_SPI3 100
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#define AWIN_A80_IRQ_NAND0 102
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#define AWIN_A80_IRQ_USB_DRD 103
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#define AWIN_A80_IRQ_USB_EHCI0 104
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#define AWIN_A80_IRQ_USB_OHCI0 105
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#define AWIN_A80_IRQ_USB_EHCI1 106
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#define AWIN_A80_IRQ_USB_EHCI2 108
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#define AWIN_A80_IRQ_USB_OHCI2 109
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#define AWIN_A80_IRQ_SS 112
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#define AWIN_A80_IRQ_TS 113
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#define AWIN_A80_IRQ_EMAC 114
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#define AWIN_A80_IRQ_MP 115
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#define AWIN_A80_IRQ_CSI0 116
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#define AWIN_A80_IRQ_CSI1 117
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#define AWIN_A80_IRQ_LCD0 118
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#define AWIN_A80_IRQ_LCD1 119
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#define AWIN_A80_IRQ_HDMI 120
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#define AWIN_A80_IRQ_MIPI_DSI 121
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#define AWIN_A80_IRQ_MIPI_CSI 122
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#define AWIN_A80_IRQ_DRC01 123
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#define AWIN_A80_IRQ_DEU01 124
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#define AWIN_A80_IRQ_DE_FE0 125
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#define AWIN_A80_IRQ_DE_FE1 126
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#define AWIN_A80_IRQ_DE_BE0 127
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#define AWIN_A80_IRQ_DE_BE1 128
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#define AWIN_A80_IRQ_GPU 129
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#define AWIN_A80_IRQ_GPU_PWR 130
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#define AWIN_A80_IRQ_FD 140
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#define AWIN_A80_IRQ_GPADC 141
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#define AWIN_A80_IRQ_THS 147
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#define AWIN_A80_IRQ_DE_BE2 148
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#define AWIN_A80_IRQ_DE_FE2 149
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#define AWIN_A80_IRQ_EDP 150
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#define AWIN_A80_IRQ_PH_EINT 152
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#define AWIN_A80_IRQ_CSI0_CCI 154
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#define AWIN_A80_IRQ_CSI1_CCI 155
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#define AWIN_A80_IRQ_CCI_400 156
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#endif /* _ARM_ALLWINNER_AWIN_INTR_H_ */
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