348 lines
10 KiB
C
348 lines
10 KiB
C
/* $NetBSD: awin_dma_a10.c,v 1.3 2014/11/12 17:38:14 jmcneill Exp $ */
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/*-
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* Copyright (c) 2014 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_ddb.h"
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: awin_dma_a10.c,v 1.3 2014/11/12 17:38:14 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/mutex.h>
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#include <arm/allwinner/awin_reg.h>
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#include <arm/allwinner/awin_var.h>
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#include <arm/allwinner/awin_dma.h>
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#define NDMA_CHANNELS 8
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#define DDMA_CHANNELS 8
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enum awin_dma_a10_type {
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CH_NDMA,
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CH_DDMA
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};
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struct awin_dma_a10_channel {
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struct awin_dma_softc *ch_sc;
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uint8_t ch_index;
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enum awin_dma_a10_type ch_type;
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void (*ch_callback)(void *);
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void *ch_callbackarg;
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uint32_t ch_regoff;
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};
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#define DMA_READ(sc, reg) \
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bus_space_read_4((sc)->sc_bst, (sc)->sc_bsh, (reg))
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#define DMA_WRITE(sc, reg, val) \
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bus_space_write_4((sc)->sc_bst, (sc)->sc_bsh, (reg), (val))
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#define DMACH_READ(ch, reg) \
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DMA_READ((ch)->ch_sc, (reg) + (ch)->ch_regoff)
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#define DMACH_WRITE(ch, reg, val) \
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DMA_WRITE((ch)->ch_sc, (reg) + (ch)->ch_regoff, (val))
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static kmutex_t awin_dma_a10_lock;
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static struct awin_dma_a10_channel awin_ndma_channels[NDMA_CHANNELS];
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static struct awin_dma_a10_channel awin_ddma_channels[DDMA_CHANNELS];
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static int awin_dma_a10_intr(void *);
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static void *awin_dma_a10_alloc(struct awin_dma_softc *, const char *,
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void (*)(void *), void *);
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static void awin_dma_a10_free(void *);
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static uint32_t awin_dma_a10_get_config(void *);
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static void awin_dma_a10_set_config(void *, uint32_t);
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static int awin_dma_a10_transfer(void *, paddr_t, paddr_t, size_t);
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static void awin_dma_a10_halt(void *);
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static const struct awin_dma_controller awin_dma_a10_controller = {
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.dma_alloc = awin_dma_a10_alloc,
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.dma_free = awin_dma_a10_free,
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.dma_get_config = awin_dma_a10_get_config,
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.dma_set_config = awin_dma_a10_set_config,
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.dma_transfer = awin_dma_a10_transfer,
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.dma_halt = awin_dma_a10_halt,
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};
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void
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awin_dma_a10_attach(struct awin_dma_softc *sc, struct awinio_attach_args *aio,
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const struct awin_locators * const loc)
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{
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unsigned int index;
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sc->sc_dc = &awin_dma_a10_controller;
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mutex_init(&awin_dma_a10_lock, MUTEX_DEFAULT, IPL_SCHED);
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awin_reg_set_clear(aio->aio_core_bst, aio->aio_ccm_bsh,
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AWIN_AHB_GATING0_REG, AWIN_AHB_GATING0_DMA, 0);
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DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, 0);
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DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, ~0);
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for (index = 0; index < NDMA_CHANNELS; index++) {
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awin_ndma_channels[index].ch_sc = sc;
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awin_ndma_channels[index].ch_index = index;
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awin_ndma_channels[index].ch_type = CH_NDMA;
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awin_ndma_channels[index].ch_callback = NULL;
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awin_ndma_channels[index].ch_callbackarg = NULL;
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awin_ndma_channels[index].ch_regoff = AWIN_NDMA_REG(index);
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DMACH_WRITE(&awin_ndma_channels[index], AWIN_NDMA_CTL_REG, 0);
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}
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for (index = 0; index < DDMA_CHANNELS; index++) {
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awin_ddma_channels[index].ch_sc = sc;
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awin_ddma_channels[index].ch_index = index;
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awin_ddma_channels[index].ch_type = CH_DDMA;
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awin_ddma_channels[index].ch_callback = NULL;
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awin_ddma_channels[index].ch_callbackarg = NULL;
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awin_ddma_channels[index].ch_regoff = AWIN_DDMA_REG(index);
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DMACH_WRITE(&awin_ddma_channels[index], AWIN_DDMA_CTL_REG, 0);
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}
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sc->sc_ih = intr_establish(loc->loc_intr, IPL_SCHED, IST_LEVEL,
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awin_dma_a10_intr, sc);
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if (sc->sc_ih == NULL) {
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aprint_error_dev(sc->sc_dev,
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"couldn't establish interrupt %d\n", loc->loc_intr);
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return;
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}
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aprint_normal_dev(sc->sc_dev, "interrupting on irq %d\n",
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loc->loc_intr);
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}
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static int
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awin_dma_a10_intr(void *priv)
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{
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struct awin_dma_softc *sc = priv;
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uint32_t sta, bit, mask;
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uint8_t index;
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sta = DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG);
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if (!sta)
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return 0;
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DMA_WRITE(sc, AWIN_DMA_IRQ_PEND_STA_REG, sta);
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while ((bit = ffs(sta & AWIN_DMA_IRQ_END_MASK)) != 0) {
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mask = __BIT(bit - 1);
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sta &= ~mask;
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index = ((bit - 1) / 2) & 7;
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if (mask & AWIN_DMA_IRQ_NDMA) {
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if (awin_ndma_channels[index].ch_callback == NULL)
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continue;
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awin_ndma_channels[index].ch_callback(
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awin_ndma_channels[index].ch_callbackarg);
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} else {
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if (awin_ddma_channels[index].ch_callback == NULL)
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continue;
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awin_ddma_channels[index].ch_callback(
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awin_ddma_channels[index].ch_callbackarg);
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}
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}
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return 1;
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}
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static void *
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awin_dma_a10_alloc(struct awin_dma_softc *sc, const char *type,
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void (*cb)(void *), void *cbarg)
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{
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struct awin_dma_a10_channel *ch_list;
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struct awin_dma_a10_channel *ch = NULL;
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uint32_t irqen;
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uint8_t ch_count, index;
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if (strcmp(type, "ddma") == 0 ||
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strcmp(type, "hdmiaudio") == 0) {
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ch_list = awin_ddma_channels;
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ch_count = DDMA_CHANNELS;
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} else {
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ch_list = awin_ndma_channels;
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ch_count = NDMA_CHANNELS;
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}
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mutex_enter(&awin_dma_a10_lock);
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for (index = 0; index < ch_count; index++) {
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if (ch_list[index].ch_callback == NULL) {
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ch = &ch_list[index];
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ch->ch_callback = cb;
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ch->ch_callbackarg = cbarg;
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irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
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if (ch->ch_type == CH_NDMA)
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irqen |= AWIN_DMA_IRQ_NDMA_END(index);
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else
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irqen |= AWIN_DMA_IRQ_DDMA_END(index);
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DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
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break;
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}
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}
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mutex_exit(&awin_dma_a10_lock);
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return ch;
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}
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static void
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awin_dma_a10_free(void *priv)
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{
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struct awin_dma_a10_channel *ch = priv;
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struct awin_dma_softc *sc = ch->ch_sc;
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uint32_t irqen, cfg;
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irqen = DMA_READ(sc, AWIN_DMA_IRQ_EN_REG);
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cfg = awin_dma_a10_get_config(ch);
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if (ch->ch_type == CH_NDMA) {
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irqen &= ~AWIN_DMA_IRQ_NDMA_END(ch->ch_index);
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cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
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} else {
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irqen &= ~AWIN_DMA_IRQ_DDMA_END(ch->ch_index);
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cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
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}
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awin_dma_a10_set_config(ch, cfg);
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DMA_WRITE(sc, AWIN_DMA_IRQ_EN_REG, irqen);
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mutex_enter(&awin_dma_a10_lock);
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ch->ch_callback = NULL;
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ch->ch_callbackarg = NULL;
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mutex_exit(&awin_dma_a10_lock);
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}
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static uint32_t
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awin_dma_a10_get_config(void *priv)
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{
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struct awin_dma_a10_channel *ch = priv;
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if (ch->ch_type == CH_NDMA) {
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return DMACH_READ(ch, AWIN_NDMA_CTL_REG);
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} else {
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return DMACH_READ(ch, AWIN_DDMA_CTL_REG);
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}
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}
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static void
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awin_dma_a10_set_config(void *priv, uint32_t val)
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{
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struct awin_dma_a10_channel *ch = priv;
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if (ch->ch_type == CH_NDMA) {
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DMACH_WRITE(ch, AWIN_NDMA_CTL_REG, val);
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} else {
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DMACH_WRITE(ch, AWIN_DDMA_CTL_REG, val);
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}
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}
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static int
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awin_dma_a10_transfer(void *priv, paddr_t src, paddr_t dst,
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size_t nbytes)
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{
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struct awin_dma_a10_channel *ch = priv;
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uint32_t cfg;
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cfg = awin_dma_a10_get_config(ch);
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if (ch->ch_type == CH_NDMA) {
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if (cfg & AWIN_NDMA_CTL_DMA_LOADING)
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return EBUSY;
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DMACH_WRITE(ch, AWIN_NDMA_SRC_ADDR_REG, src);
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DMACH_WRITE(ch, AWIN_NDMA_DEST_ADDR_REG, dst);
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DMACH_WRITE(ch, AWIN_NDMA_BC_REG, nbytes);
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cfg |= AWIN_NDMA_CTL_DMA_LOADING;
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awin_dma_a10_set_config(ch, cfg);
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} else {
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if (cfg & AWIN_DDMA_CTL_DMA_LOADING)
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return EBUSY;
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DMACH_WRITE(ch, AWIN_DDMA_SRC_START_ADDR_REG, src);
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DMACH_WRITE(ch, AWIN_DDMA_DEST_START_ADDR_REG, dst);
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DMACH_WRITE(ch, AWIN_DDMA_BC_REG, nbytes);
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DMACH_WRITE(ch, AWIN_DDMA_PARA_REG,
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__SHIFTIN(31, AWIN_DDMA_PARA_DST_DATA_BLK_SIZ) |
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__SHIFTIN(7, AWIN_DDMA_PARA_DST_WAIT_CYC) |
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__SHIFTIN(31, AWIN_DDMA_PARA_SRC_DATA_BLK_SIZ) |
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__SHIFTIN(7, AWIN_DDMA_PARA_SRC_WAIT_CYC));
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cfg |= AWIN_DDMA_CTL_DMA_LOADING;
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awin_dma_a10_set_config(ch, cfg);
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}
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return 0;
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}
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static void
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awin_dma_a10_halt(void *priv)
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{
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struct awin_dma_a10_channel *ch = priv;
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uint32_t cfg;
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cfg = awin_dma_a10_get_config(ch);
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if (ch->ch_type == CH_NDMA) {
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cfg &= ~AWIN_NDMA_CTL_DMA_LOADING;
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} else {
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cfg &= ~AWIN_DDMA_CTL_DMA_LOADING;
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}
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awin_dma_a10_set_config(ch, cfg);
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}
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#if defined(DDB)
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void
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awin_dma_a10_dump_regs(struct awin_dma_softc *sc)
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{
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int i;
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printf("IRQ_EN: %08X\n", DMA_READ(sc, AWIN_DMA_IRQ_EN_REG));
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printf("PEND_STA: %08X\n",
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DMA_READ(sc, AWIN_DMA_IRQ_PEND_STA_REG));
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for (i = 0; i < NDMA_CHANNELS; i++) {
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printf("NDMA%d CTL: %08X\n", i,
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DMA_READ(sc, AWIN_NDMA_REG(i) + AWIN_NDMA_CTL_REG));
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printf("NDMA%d SRC_ADDR: %08X\n", i,
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DMA_READ(sc, AWIN_NDMA_REG(i) + AWIN_NDMA_SRC_ADDR_REG));
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printf("NDMA%d DEST_ADDR: %08X\n", i,
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DMA_READ(sc, AWIN_NDMA_REG(i) + AWIN_NDMA_DEST_ADDR_REG));
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printf("NDMA%d BC: %08X\n", i,
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DMA_READ(sc, AWIN_NDMA_REG(i) + AWIN_NDMA_BC_REG));
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}
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for (i = 0; i < DDMA_CHANNELS; i++) {
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printf("DDMA%d CTL: %08X\n", i,
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DMA_READ(sc, AWIN_DDMA_REG(i) + AWIN_DDMA_CTL_REG));
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printf("DDMA%d SRC_ADDR: %08X\n", i,
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DMA_READ(sc, AWIN_DDMA_REG(i) + AWIN_DDMA_SRC_START_ADDR_REG));
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printf("DDMA%d DEST_ADDR: %08X\n", i,
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DMA_READ(sc, AWIN_DDMA_REG(i) + AWIN_DDMA_DEST_START_ADDR_REG));
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printf("DDMA%d BC: %08X\n", i,
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DMA_READ(sc, AWIN_DDMA_REG(i) + AWIN_DDMA_BC_REG));
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printf("DDMA%d PARA: %08X\n", i,
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DMA_READ(sc, AWIN_DDMA_REG(i) + AWIN_DDMA_PARA_REG));
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}
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}
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#endif
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