603 lines
21 KiB
C
603 lines
21 KiB
C
/* $NetBSD: rtl81x9reg.h,v 1.47 2015/08/28 13:20:46 nonaka Exp $ */
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/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* FreeBSD Id: if_rlreg.h,v 1.9 1999/06/20 18:56:09 wpaul Exp
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*/
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/*
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* RealTek 8129/8139 register offsets
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*/
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#define RTK_IDR0 0x0000 /* ID register 0 (station addr) */
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#define RTK_IDR1 0x0001 /* Must use 32-bit accesses (?) */
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#define RTK_IDR2 0x0002
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#define RTK_IDR3 0x0003
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#define RTK_IDR4 0x0004
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#define RTK_IDR5 0x0005
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/* 0006-0007 reserved */
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#define RTK_MAR0 0x0008 /* Multicast hash table */
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#define RTK_MAR1 0x0009
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#define RTK_MAR2 0x000A
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#define RTK_MAR3 0x000B
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#define RTK_MAR4 0x000C
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#define RTK_MAR5 0x000D
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#define RTK_MAR6 0x000E
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#define RTK_MAR7 0x000F
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#define RTK_TXSTAT0 0x0010 /* status of TX descriptor 0 */
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#define RTK_TXSTAT1 0x0014 /* status of TX descriptor 1 */
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#define RTK_TXSTAT2 0x0018 /* status of TX descriptor 2 */
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#define RTK_TXSTAT3 0x001C /* status of TX descriptor 3 */
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#define RTK_TXADDR0 0x0020 /* address of TX descriptor 0 */
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#define RTK_TXADDR1 0x0024 /* address of TX descriptor 1 */
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#define RTK_TXADDR2 0x0028 /* address of TX descriptor 2 */
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#define RTK_TXADDR3 0x002C /* address of TX descriptor 3 */
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#define RTK_RXADDR 0x0030 /* RX ring start address */
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#define RTK_RX_EARLY_BYTES 0x0034 /* RX early byte count */
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#define RTK_RX_EARLY_STAT 0x0036 /* RX early status */
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#define RTK_COMMAND 0x0037 /* command register */
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#define RTK_CURRXADDR 0x0038 /* current address of packet read */
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#define RTK_CURRXBUF 0x003A /* current RX buffer address */
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#define RTK_IMR 0x003C /* interrupt mask register */
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#define RTK_ISR 0x003E /* interrupt status register */
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#define RTK_TXCFG 0x0040 /* transmit config */
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#define RTK_RXCFG 0x0044 /* receive config */
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#define RTK_TIMERCNT 0x0048 /* timer count register */
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#define RTK_MISSEDPKT 0x004C /* missed packet counter */
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#define RTK_EECMD 0x0050 /* EEPROM command register */
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#define RTK_CFG0 0x0051 /* config register #0 */
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#define RTK_CFG1 0x0052 /* config register #1 */
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/* 0053-0057 reserved */
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#define RTK_MEDIASTAT 0x0058 /* media status register (8139) */
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/* 0059-005A reserved */
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#define RTK_MII 0x005A /* 8129 chip only */
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#define RTK_HALTCLK 0x005B
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#define RTK_MULTIINTR 0x005C /* multiple interrupt */
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#define RTK_PCIREV 0x005E /* PCI revision value */
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/* 005F reserved */
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#define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */
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/* Direct PHY access registers only available on 8139 */
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#define RTK_BMCR 0x0062 /* PHY basic mode control */
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#define RTK_BMSR 0x0064 /* PHY basic mode status */
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#define RTK_ANAR 0x0066 /* PHY autoneg advert */
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#define RTK_LPAR 0x0068 /* PHY link partner ability */
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#define RTK_ANER 0x006A /* PHY autoneg expansion */
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#define RTK_DISCCNT 0x006C /* disconnect counter */
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#define RTK_FALSECAR 0x006E /* false carrier counter */
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#define RTK_NWAYTST 0x0070 /* NWAY test register */
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#define RTK_RX_ER 0x0072 /* RX_ER counter */
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#define RTK_CSCFG 0x0074 /* CS configuration register */
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/*
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* When operating in special C+ mode, some of the registers in an
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* 8139C+ chip have different definitions. These are also used for
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* the 8169 gigE chip.
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*/
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#define RTK_DUMPSTATS_LO 0x0010 /* counter dump command register */
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#define RTK_DUMPSTATS_HI 0x0014 /* counter dump command register */
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#define RTK_TXLIST_ADDR_LO 0x0020 /* 64 bits, 256 byte alignment */
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#define RTK_TXLIST_ADDR_HI 0x0024 /* 64 bits, 256 byte alignment */
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#define RTK_TXLIST_ADDR_HPRIO_LO 0x0028 /* 64 bits, 256 byte aligned */
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#define RTK_TXLIST_ADDR_HPRIO_HI 0x002C /* 64 bits, 256 byte aligned */
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#define RTK_CFG2 0x0053
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#define RTK_TIMERINT 0x0054 /* interrupt on timer expire */
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#define RTK_TXSTART 0x00D9 /* 8 bits */
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#define RTK_CPLUS_CMD 0x00E0 /* 16 bits */
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#define RTK_RXLIST_ADDR_LO 0x00E4 /* 64 bits, 256 byte alignment */
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#define RTK_RXLIST_ADDR_HI 0x00E8 /* 64 bits, 256 byte alignment */
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#define RTK_EARLY_TX_THRESH 0x00EC /* 8 bits */
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/*
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* Registers specific to the 8169 gigE chip
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*/
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#define RTK_GTXSTART 0x0038 /* 8 bits */
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#define RTK_TIMERINT_8169 0x0058 /* different offset than 8139 */
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#define RTK_PHYAR 0x0060
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#define RTK_CSIDR 0x0064
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#define RTK_CSIAR 0x0068
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#define RTK_TBI_LPAR 0x006A
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#define RTK_GMEDIASTAT 0x006C /* 8 bits */
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#define RTK_PMCH 0x006F /* 8 bits */
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#define RTK_EPHYAR 0x0080
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#define RTK_LDPS 0x0082 /* Link Down Power Saving */
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#define RTK_DBG_REG 0x00D1
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#define RTK_MAXRXPKTLEN 0x00DA /* 16 bits, chip multiplies by 8 */
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#define RTK_IM 0x00E2
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#define RTK_MISC 0x00F0
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/*
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* TX config register bits
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*/
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#define RTK_TXCFG_CLRABRT 0x00000001 /* retransmit aborted pkt */
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#define RTK_TXCFG_MAXDMA 0x00000700 /* max DMA burst size */
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#define RTK_TXCFG_CRCAPPEND 0x00010000 /* CRC append (0 = yes) */
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#define RTK_TXCFG_LOOPBKTST 0x00060000 /* loopback test */
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#define RTK_TXCFG_IFG2 0x00080000 /* 8169 only */
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#define RTK_TXCFG_IFG 0x03000000 /* interframe gap */
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#define RTK_TXCFG_HWREV 0x7CC00000
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#define RTK_LOOPTEST_OFF 0x00000000
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#define RTK_LOOPTEST_ON 0x00020000
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#define RTK_LOOPTEST_ON_CPLUS 0x00060000
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/* Known revision codes. */
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#define RTK_HWREV_8169 0x00000000
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#define RTK_HWREV_8110S 0x00800000
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#define RTK_HWREV_8169S 0x04000000
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#define RTK_HWREV_8169_8110SB 0x10000000
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#define RTK_HWREV_8169_8110SC 0x18000000
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#define RTK_HWREV_8102EL 0x24800000
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#define RTK_HWREV_8103E 0x24C00000
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#define RTK_HWREV_8168D 0x28000000
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#define RTK_HWREV_8168DP 0x28800000
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#define RTK_HWREV_8168E 0x2C000000
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#define RTK_HWREV_8168E_VL 0x2C800000
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#define RTK_HWREV_8168_SPIN1 0x30000000
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#define RTK_HWREV_8168G 0x4c000000
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#define RTK_HWREV_8168G_SPIN1 0x4c100000
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#define RTK_HWREV_8168G_SPIN2 0x50900000
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#define RTK_HWREV_8168G_SPIN4 0x5c800000
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#define RTK_HWREV_8168GU 0x50800000
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#define RTK_HWREV_8100E 0x30800000
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#define RTK_HWREV_8101E 0x34000000
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#define RTK_HWREV_8102E 0x34800000
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#define RTK_HWREV_8168_SPIN2 0x38000000
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#define RTK_HWREV_8168_SPIN3 0x38400000
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#define RTK_HWREV_8100E_SPIN2 0x38800000
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#define RTK_HWREV_8168C 0x3C000000
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#define RTK_HWREV_8168C_SPIN2 0x3C400000
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#define RTK_HWREV_8168CP 0x3C800000
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#define RTK_HWREV_8168F 0x48000000
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#define RTK_HWREV_8168H 0x54000000
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#define RTK_HWREV_8168H_SPIN1 0x54100000
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#define RTK_HWREV_8139 0x60000000
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#define RTK_HWREV_8139A 0x70000000
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#define RTK_HWREV_8139AG 0x70800000
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#define RTK_HWREV_8139B 0x78000000
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#define RTK_HWREV_8130 0x7C000000
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#define RTK_HWREV_8139C 0x74000000
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#define RTK_HWREV_8139D 0x74400000
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#define RTK_HWREV_8139CPLUS 0x74800000
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#define RTK_HWREV_8101 0x74c00000
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#define RTK_HWREV_8100 0x78800000
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#define RTK_HWREV_8169_8110SBL 0x7cc00000
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#define RTK_TXDMA_16BYTES 0x00000000
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#define RTK_TXDMA_32BYTES 0x00000100
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#define RTK_TXDMA_64BYTES 0x00000200
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#define RTK_TXDMA_128BYTES 0x00000300
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#define RTK_TXDMA_256BYTES 0x00000400
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#define RTK_TXDMA_512BYTES 0x00000500
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#define RTK_TXDMA_1024BYTES 0x00000600
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#define RTK_TXDMA_2048BYTES 0x00000700
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/*
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* Transmit descriptor status register bits.
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*/
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#define RTK_TXSTAT_LENMASK 0x00001FFF
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#define RTK_TXSTAT_OWN 0x00002000
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#define RTK_TXSTAT_TX_UNDERRUN 0x00004000
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#define RTK_TXSTAT_TX_OK 0x00008000
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#define RTK_TXSTAT_EARLY_THRESH 0x003F0000
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#define RTK_TXSTAT_COLLCNT 0x0F000000
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#define RTK_TXSTAT_CARR_HBEAT 0x10000000
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#define RTK_TXSTAT_OUTOFWIN 0x20000000
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#define RTK_TXSTAT_TXABRT 0x40000000
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#define RTK_TXSTAT_CARRLOSS 0x80000000
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#define RTK_TXSTAT_THRESH(x) (((x) << 16) & RTK_TXSTAT_EARLY_THRESH)
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#define RTK_TXTH_256 8 /* (x) * 32 bytes */
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#define RTK_TXTH_1536 48
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/* MISC register */
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#define RTK_MISC_TXPLA_RST __BIT(29)
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#define RTK_MISC_DISABLE_LAN_EN __BIT(23) /* Enable GPIO pin */
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#define RTK_MISC_PWM_EN __BIT(22)
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#define RTK_MISC_RXDV_GATED_EN __BIT(19)
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#define RTK_MISC_EARLY_TALLY_EN __BIT(16)
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/*
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* Interrupt status register bits.
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*/
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#define RTK_ISR_RX_OK 0x0001
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#define RTK_ISR_RX_ERR 0x0002
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#define RTK_ISR_TX_OK 0x0004
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#define RTK_ISR_TX_ERR 0x0008
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#define RTK_ISR_RX_OVERRUN 0x0010
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#define RTK_ISR_PKT_UNDERRUN 0x0020
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#define RTK_ISR_LINKCHG 0x0020 /* 8169 only */
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#define RTK_ISR_FIFO_OFLOW 0x0040 /* 8139 only */
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#define RTK_ISR_TX_DESC_UNAVAIL 0x0080 /* C+ only */
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#define RTK_ISR_SWI 0x0100 /* C+ only */
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#define RTK_ISR_CABLE_LEN_CHGD 0x2000
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#define RTK_ISR_PCS_TIMEOUT 0x4000 /* 8129 only */
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#define RTK_ISR_TIMEOUT_EXPIRED 0x4000
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#define RTK_ISR_SYSTEM_ERR 0x8000
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#define RTK_INTRS \
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(RTK_ISR_TX_OK|RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \
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RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
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RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR)
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#define RTK_INTRS_CPLUS \
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(RTK_ISR_RX_OK|RTK_ISR_RX_ERR|RTK_ISR_TX_ERR| \
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RTK_ISR_RX_OVERRUN|RTK_ISR_PKT_UNDERRUN|RTK_ISR_FIFO_OFLOW| \
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RTK_ISR_PCS_TIMEOUT|RTK_ISR_SYSTEM_ERR|RTK_ISR_TIMEOUT_EXPIRED)
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/*
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* Media status register. (8139 only)
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*/
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#define RTK_MEDIASTAT_RXPAUSE 0x01
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#define RTK_MEDIASTAT_TXPAUSE 0x02
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#define RTK_MEDIASTAT_LINK 0x04
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#define RTK_MEDIASTAT_SPEED10 0x08
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#define RTK_MEDIASTAT_RXFLOWCTL 0x40 /* duplex mode */
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#define RTK_MEDIASTAT_TXFLOWCTL 0x80 /* duplex mode */
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/*
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* Receive config register.
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*/
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#define RTK_RXCFG_RX_ALLPHYS 0x00000001 /* accept all nodes */
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#define RTK_RXCFG_RX_INDIV 0x00000002 /* match filter */
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#define RTK_RXCFG_RX_MULTI 0x00000004 /* accept all multicast */
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#define RTK_RXCFG_RX_BROAD 0x00000008 /* accept all broadcast */
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#define RTK_RXCFG_RX_RUNT 0x00000010
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#define RTK_RXCFG_RX_ERRPKT 0x00000020
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#define RTK_RXCFG_WRAP 0x00000080
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#define RTK_RXCFG_MAXDMA 0x00000700
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#define RTK_RXCFG_BUFSZ 0x00001800
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#define RTK_RXCFG_FIFOTHRESH 0x0000E000
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#define RTK_RXCFG_EARLYTHRESH 0x07000000
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#define RTK_RXDMA_16BYTES 0x00000000
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#define RTK_RXDMA_32BYTES 0x00000100
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#define RTK_RXDMA_64BYTES 0x00000200
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#define RTK_RXDMA_128BYTES 0x00000300
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#define RTK_RXDMA_256BYTES 0x00000400
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#define RTK_RXDMA_512BYTES 0x00000500
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#define RTK_RXDMA_1024BYTES 0x00000600
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#define RTK_RXDMA_UNLIMITED 0x00000700
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#define RTK_RXBUF_8 0x00000000
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#define RTK_RXBUF_16 0x00000800
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#define RTK_RXBUF_32 0x00001000
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#define RTK_RXBUF_64 0x00001800
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#define RTK_RXBUF_LEN(x) (1 << (((x) >> 11) + 13))
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#define RTK_RXFIFO_16BYTES 0x00000000
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#define RTK_RXFIFO_32BYTES 0x00002000
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#define RTK_RXFIFO_64BYTES 0x00004000
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#define RTK_RXFIFO_128BYTES 0x00006000
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#define RTK_RXFIFO_256BYTES 0x00008000
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#define RTK_RXFIFO_512BYTES 0x0000A000
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#define RTK_RXFIFO_1024BYTES 0x0000C000
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#define RTK_RXFIFO_NOTHRESH 0x0000E000
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/*
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* Bits in RX status header (included with RX'ed packet
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* in ring buffer).
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*/
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#define RTK_RXSTAT_RXOK 0x00000001
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#define RTK_RXSTAT_ALIGNERR 0x00000002
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#define RTK_RXSTAT_CRCERR 0x00000004
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#define RTK_RXSTAT_GIANT 0x00000008
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#define RTK_RXSTAT_RUNT 0x00000010
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#define RTK_RXSTAT_BADSYM 0x00000020
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#define RTK_RXSTAT_BROAD 0x00002000
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#define RTK_RXSTAT_INDIV 0x00004000
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#define RTK_RXSTAT_MULTI 0x00008000
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#define RTK_RXSTAT_LENMASK 0xFFFF0000
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#define RTK_RXSTAT_UNFINISHED 0xFFF0 /* DMA still in progress */
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/*
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* Command register.
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*/
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#define RTK_CMD_EMPTY_RXBUF 0x0001
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#define RTK_CMD_TX_ENB 0x0004
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#define RTK_CMD_RX_ENB 0x0008
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#define RTK_CMD_RESET 0x0010
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#define RTK_CMD_STOPREQ 0x0080
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/*
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* EEPROM control register
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*/
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#define RTK_EE_DATAOUT 0x01 /* Data out */
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#define RTK_EE_DATAIN 0x02 /* Data in */
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#define RTK_EE_CLK 0x04 /* clock */
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#define RTK_EE_SEL 0x08 /* chip select */
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#define RTK_EE_MODE (0x40|0x80)
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#define RTK_EEMODE_OFF 0x00
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#define RTK_EEMODE_AUTOLOAD 0x40
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#define RTK_EEMODE_PROGRAM 0x80
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#define RTK_EEMODE_WRITECFG (0x80|0x40)
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/* 9346/9356 EEPROM commands */
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#define RTK_EEADDR_LEN0 6 /* 9346 */
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#define RTK_EEADDR_LEN1 8 /* 9356 */
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#define RTK_EECMD_LEN 4
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#define RTK_EECMD_WRITE 0x5 /* 0101b */
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#define RTK_EECMD_READ 0x6 /* 0110b */
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#define RTK_EECMD_ERASE 0x7 /* 0111b */
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#define RTK_EE_ID 0x00
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#define RTK_EE_PCI_VID 0x01
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#define RTK_EE_PCI_DID 0x02
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/* Location of station address inside EEPROM */
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#define RTK_EE_EADDR0 0x07
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#define RTK_EE_EADDR1 0x08
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#define RTK_EE_EADDR2 0x09
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/*
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* MII register (8129 only)
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*/
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#define RTK_MII_CLK 0x01
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#define RTK_MII_DATAIN 0x02
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#define RTK_MII_DATAOUT 0x04
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#define RTK_MII_DIR 0x80 /* 0 == input, 1 == output */
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/*
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* Config 0 register
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*/
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#define RTK_CFG0_ROM0 0x01
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#define RTK_CFG0_ROM1 0x02
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#define RTK_CFG0_ROM2 0x04
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#define RTK_CFG0_PL0 0x08
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#define RTK_CFG0_PL1 0x10
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#define RTK_CFG0_10MBPS 0x20 /* 10 Mbps internal mode */
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#define RTK_CFG0_PCS 0x40
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#define RTK_CFG0_SCR 0x80
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/*
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* Config 1 register
|
|
*/
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|
#define RTK_CFG1_PWRDWN 0x01
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#define RTK_CFG1_SLEEP 0x02
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#define RTK_CFG1_IOMAP 0x04
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#define RTK_CFG1_MEMMAP 0x08
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#define RTK_CFG1_RSVD 0x10
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#define RTK_CFG1_DRVLOAD 0x20
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#define RTK_CFG1_LED0 0x40
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#define RTK_CFG1_FULLDUPLEX 0x40 /* 8129 only */
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#define RTK_CFG1_LED1 0x80
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|
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/*
|
|
* 8139C+ register definitions
|
|
*/
|
|
|
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/* RTK_DUMPSTATS_LO register */
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#define RTK_DUMPSTATS_START 0x00000008
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|
|
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/* Transmit start register */
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|
|
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#define RTK_TXSTART_SWI 0x01 /* generate TX interrupt */
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#define RTK_TXSTART_START 0x40 /* start normal queue transmit */
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#define RTK_TXSTART_HPRIO_START 0x80 /* start hi prio queue transmit */
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|
|
|
/*
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* Config 2 register, 8139C+/8169/8169S/8110S only
|
|
*/
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#define RTK_CFG2_BUSFREQ 0x07
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#define RTK_CFG2_BUSWIDTH 0x08
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#define RTK_CFG2_AUXPWRSTS 0x10
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|
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#define RTK_BUSFREQ_33MHZ 0x00
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#define RTK_BUSFREQ_66MHZ 0x01
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|
|
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#define RTK_BUSWIDTH_32BITS 0x00
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#define RTK_BUSWIDTH_64BITS 0x08
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|
|
|
/* C+ mode command register */
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|
|
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#define RE_CPLUSCMD_TXENB 0x0001 /* enable C+ transmit mode */
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#define RE_CPLUSCMD_RXENB 0x0002 /* enable C+ receive mode */
|
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#define RE_CPLUSCMD_PCI_MRW 0x0008 /* enable PCI multi-read/write */
|
|
#define RE_CPLUSCMD_PCI_DAC 0x0010 /* PCI dual-address cycle only */
|
|
#define RE_CPLUSCMD_RXCSUM_ENB 0x0020 /* enable RX checksum offload */
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#define RE_CPLUSCMD_VLANSTRIP 0x0040 /* enable VLAN tag stripping */
|
|
#define RE_CPLUSCMD_MACSTAT_DIS 0x0080 /* 8168B/C/CP */
|
|
#define RE_CPLUSCMD_ASF 0x0100 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_DBG_SEL 0x0200 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_FORCE_TXFC 0x0400 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_FORCE_RXFC 0x0800 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_FORCE_HDPX 0x1000 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_NORMAL_MODE 0x2000 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_DBG_ENB 0x4000 /* 8168C/CP */
|
|
#define RE_CPLUSCMD_BIST_ENB 0x8000 /* 8168C/CP */
|
|
|
|
/* C+ early transmit threshold */
|
|
|
|
#define RTK_EARLYTXTHRESH_CNT 0x003F /* byte count times 8 */
|
|
|
|
/*
|
|
* Gigabit PHY access register (8169 only)
|
|
*/
|
|
|
|
#define RTK_PHYAR_PHYDATA 0x0000FFFF
|
|
#define RTK_PHYAR_PHYREG 0x001F0000
|
|
#define RTK_PHYAR_BUSY 0x80000000
|
|
|
|
/*
|
|
* Gigabit media status (8169 only)
|
|
*/
|
|
#define RTK_GMEDIASTAT_FDX 0x01 /* full duplex */
|
|
#define RTK_GMEDIASTAT_LINK 0x02 /* link up */
|
|
#define RTK_GMEDIASTAT_10MBPS 0x04 /* 10mps link */
|
|
#define RTK_GMEDIASTAT_100MBPS 0x08 /* 100mbps link */
|
|
#define RTK_GMEDIASTAT_1000MBPS 0x10 /* gigE link */
|
|
#define RTK_GMEDIASTAT_RXFLOW 0x20 /* RX flow control on */
|
|
#define RTK_GMEDIASTAT_TXFLOW 0x40 /* TX flow control on */
|
|
#define RTK_GMEDIASTAT_TBI 0x80 /* TBI enabled */
|
|
|
|
|
|
#define RTK_TX_EARLYTHRESH ((256 / 32) << 16)
|
|
#define RTK_RX_FIFOTHRESH RTK_RXFIFO_256BYTES
|
|
#define RTK_RX_MAXDMA RTK_RXDMA_256BYTES
|
|
#define RTK_TX_MAXDMA RTK_TXDMA_256BYTES
|
|
|
|
#define RTK_RXCFG_CONFIG (RTK_RX_FIFOTHRESH|RTK_RX_MAXDMA|RTK_RX_BUF_SZ)
|
|
#define RTK_TXCFG_CONFIG (RTK_TXCFG_IFG|RTK_TX_MAXDMA)
|
|
|
|
#define RE_RX_FIFOTHRESH RTK_RXFIFO_NOTHRESH
|
|
#define RE_RX_MAXDMA RTK_RXDMA_UNLIMITED
|
|
#define RE_TX_MAXDMA RTK_TXDMA_2048BYTES
|
|
|
|
#define RE_RXCFG_CONFIG (RE_RX_FIFOTHRESH|RE_RX_MAXDMA|RTK_RX_BUF_SZ)
|
|
#define RE_TXCFG_CONFIG (RTK_TXCFG_IFG|RE_TX_MAXDMA)
|
|
|
|
/*
|
|
* RX/TX descriptor definition. When large send mode is enabled, the
|
|
* lower 11 bits of the TX rtk_cmd word are used to hold the MSS, and
|
|
* the checksum offload bits are disabled. The structure layout is
|
|
* the same for RX and TX descriptors
|
|
*/
|
|
|
|
struct re_desc {
|
|
volatile uint32_t re_cmdstat;
|
|
volatile uint32_t re_vlanctl;
|
|
volatile uint32_t re_bufaddr_lo;
|
|
volatile uint32_t re_bufaddr_hi;
|
|
};
|
|
|
|
#define RE_TDESC_CMD_FRAGLEN 0x0000FFFF
|
|
#define RE_TDESC_CMD_TCPCSUM 0x00010000 /* TCP checksum enable */
|
|
#define RE_TDESC_CMD_UDPCSUM 0x00020000 /* UDP checksum enable */
|
|
#define RE_TDESC_CMD_IPCSUM 0x00040000 /* IP header checksum enable */
|
|
#define RE_TDESC_CMD_MSSVAL 0x07FF0000 /* Large send MSS value */
|
|
#define RE_TDESC_CMD_MSSVAL_SHIFT 16 /* Shift of the above */
|
|
#define RE_TDESC_CMD_LGSEND 0x08000000 /* TCP large send enb */
|
|
#define RE_TDESC_CMD_EOF 0x10000000 /* end of frame marker */
|
|
#define RE_TDESC_CMD_SOF 0x20000000 /* start of frame marker */
|
|
#define RE_TDESC_CMD_EOR 0x40000000 /* end of ring marker */
|
|
#define RE_TDESC_CMD_OWN 0x80000000 /* chip owns descriptor */
|
|
|
|
#define RE_TDESC_VLANCTL_TAG 0x00020000 /* Insert VLAN tag */
|
|
#define RE_TDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
|
|
#define RE_TDESC_VLANCTL_UDPCSUM 0x80000000 /* DESCV2 UDP cksum enable */
|
|
#define RE_TDESC_VLANCTL_TCPCSUM 0x40000000 /* DESCV2 TCP cksum enable */
|
|
#define RE_TDESC_VLANCTL_IPCSUM 0x20000000 /* DESCV2 IP hdr cksum enable */
|
|
|
|
/*
|
|
* Error bits are valid only on the last descriptor of a frame
|
|
* (i.e. RE_TDESC_CMD_EOF == 1)
|
|
*/
|
|
|
|
#define RE_TDESC_STAT_COLCNT 0x000F0000 /* collision count */
|
|
#define RE_TDESC_STAT_EXCESSCOL 0x00100000 /* excessive collisions */
|
|
#define RE_TDESC_STAT_LINKFAIL 0x00200000 /* link faulure */
|
|
#define RE_TDESC_STAT_OWINCOL 0x00400000 /* out-of-window collision */
|
|
#define RE_TDESC_STAT_TXERRSUM 0x00800000 /* transmit error summary */
|
|
#define RE_TDESC_STAT_UNDERRUN 0x02000000 /* TX underrun occurred */
|
|
#define RE_TDESC_STAT_OWN 0x80000000
|
|
|
|
/*
|
|
* RX descriptor cmd/vlan definitions
|
|
*/
|
|
|
|
#define RE_RDESC_CMD_EOR 0x40000000
|
|
#define RE_RDESC_CMD_OWN 0x80000000
|
|
#define RE_RDESC_CMD_BUFLEN 0x00001FFF
|
|
|
|
#define RE_RDESC_STAT_OWN 0x80000000
|
|
#define RE_RDESC_STAT_EOR 0x40000000
|
|
#define RE_RDESC_STAT_SOF 0x20000000
|
|
#define RE_RDESC_STAT_EOF 0x10000000
|
|
#define RE_RDESC_STAT_FRALIGN 0x08000000 /* frame alignment error */
|
|
#define RE_RDESC_STAT_MCAST 0x04000000 /* multicast pkt received */
|
|
#define RE_RDESC_STAT_UCAST 0x02000000 /* unicast pkt received */
|
|
#define RE_RDESC_STAT_BCAST 0x01000000 /* broadcast pkt received */
|
|
#define RE_RDESC_STAT_BUFOFLOW 0x00800000 /* out of buffer space */
|
|
#define RE_RDESC_STAT_FIFOOFLOW 0x00400000 /* FIFO overrun */
|
|
#define RE_RDESC_STAT_GIANT 0x00200000 /* pkt > 4096 bytes */
|
|
#define RE_RDESC_STAT_RXERRSUM 0x00100000 /* RX error summary */
|
|
#define RE_RDESC_STAT_RUNT 0x00080000 /* runt packet received */
|
|
#define RE_RDESC_STAT_CRCERR 0x00040000 /* CRC error */
|
|
#define RE_RDESC_STAT_PROTOID 0x00030000 /* Protocol type */
|
|
#define RE_RDESC_STAT_IPSUMBAD 0x00008000 /* IP header checksum bad */
|
|
#define RE_RDESC_STAT_UDPSUMBAD 0x00004000 /* UDP checksum bad */
|
|
#define RE_RDESC_STAT_TCPSUMBAD 0x00002000 /* TCP checksum bad */
|
|
#define RE_RDESC_STAT_FRAGLEN 0x00001FFF /* RX'ed frame/frag len */
|
|
#define RE_RDESC_STAT_GFRAGLEN 0x00003FFF /* RX'ed frame/frag len */
|
|
|
|
#define RE_RDESC_VLANCTL_TAG 0x00010000 /* VLAN tag available
|
|
(re_vlandata valid)*/
|
|
#define RE_RDESC_VLANCTL_DATA 0x0000FFFF /* TAG data */
|
|
#define RE_RDESC_VLANCTL_IPV6 0x80000000 /* DESCV2 IPV6 packet */
|
|
#define RE_RDESC_VLANCTL_IPV4 0x40000000 /* DESCV2 IPV4 packet */
|
|
|
|
#define RE_PROTOID_NONIP 0x00000000
|
|
#define RE_PROTOID_TCPIP 0x00010000
|
|
#define RE_PROTOID_UDPIP 0x00020000
|
|
#define RE_PROTOID_IP 0x00030000
|
|
#define RE_TCPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \
|
|
RE_PROTOID_TCPIP)
|
|
#define RE_UDPPKT(x) (((x) & RE_RDESC_STAT_PROTOID) == \
|
|
RE_PROTOID_UDPIP)
|
|
|
|
#define RE_ADDR_LO(y) ((uint64_t)(y) & 0xFFFFFFFF)
|
|
#define RE_ADDR_HI(y) ((uint64_t)(y) >> 32)
|
|
|
|
/*
|
|
* Statistics counter structure (8139C+ and 8169 only)
|
|
*/
|
|
struct re_stats {
|
|
uint32_t re_tx_pkts_lo;
|
|
uint32_t re_tx_pkts_hi;
|
|
uint32_t re_tx_errs_lo;
|
|
uint32_t re_tx_errs_hi;
|
|
uint32_t re_tx_errs;
|
|
uint16_t re_missed_pkts;
|
|
uint16_t re_rx_framealign_errs;
|
|
uint32_t re_tx_onecoll;
|
|
uint32_t re_tx_multicolls;
|
|
uint32_t re_rx_ucasts_hi;
|
|
uint32_t re_rx_ucasts_lo;
|
|
uint32_t re_rx_bcasts_lo;
|
|
uint32_t re_rx_bcasts_hi;
|
|
uint32_t re_rx_mcasts;
|
|
uint16_t re_tx_aborts;
|
|
uint16_t re_rx_underruns;
|
|
};
|
|
|
|
#define RE_IFQ_MAXLEN 512
|
|
|
|
#define RE_JUMBO_FRAMELEN ETHER_MAX_LEN_JUMBO
|
|
#define RE_JUMBO_MTU ETHERMTU_JUMBO
|