555 lines
16 KiB
C
555 lines
16 KiB
C
/* $NetBSD: vrip.c,v 1.29 2003/07/15 02:29:36 lukem Exp $ */
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/*-
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* Copyright (c) 1999, 2002
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* Shin Takemura and PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: vrip.c,v 1.29 2003/07/15 02:29:36 lukem Exp $");
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#include "opt_vr41xx.h"
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#include "opt_tx39xx.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/reboot.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <machine/autoconf.h>
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#include <machine/platid.h>
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#include <machine/platid_mask.h>
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#include <hpcmips/vr/vr.h>
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#include <hpcmips/vr/vrcpudef.h>
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#include <hpcmips/vr/vripunit.h>
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#include <hpcmips/vr/vripif.h>
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#include <hpcmips/vr/vripreg.h>
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#include <hpcmips/vr/vripvar.h>
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#include <hpcmips/vr/icureg.h>
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#include <hpcmips/vr/cmureg.h>
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#include "locators.h"
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#ifdef VRIP_DEBUG
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#define DPRINTF_ENABLE
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#define DPRINTF_DEBUG vrip_debug
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#endif
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#define USE_HPC_DPRINTF
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#include <machine/debug.h>
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#ifdef VRIP_DEBUG
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#define DBG_BIT_PRINT(reg) if (vrip_debug) dbg_bit_print(reg);
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#define DUMP_LEVEL2MASK(sc,arg) if (vrip_debug) __vrip_dump_level2mask(sc,arg)
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#else
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#define DBG_BIT_PRINT(arg)
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#define DUMP_LEVEL2MASK(sc,arg)
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#endif
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#define VALID_UNIT(sc, unit) (0 <= (unit) && (unit) < (sc)->sc_nunits)
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#ifdef SINGLE_VRIP_BASE
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int vripmatch(struct device *, struct cfdata *, void *);
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void vripattach(struct device *, struct device *, void *);
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#endif
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int vrip_print(void *, const char *);
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int vrip_search(struct device *, struct cfdata *, void *);
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int vrip_intr(void *, u_int32_t, u_int32_t);
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int __vrip_power(vrip_chipset_tag_t, int, int);
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vrip_intr_handle_t __vrip_intr_establish(vrip_chipset_tag_t, int, int,
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int, int(*)(void*), void*);
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void __vrip_intr_disestablish(vrip_chipset_tag_t, vrip_intr_handle_t);
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void __vrip_intr_setmask1(vrip_chipset_tag_t, vrip_intr_handle_t, int);
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void __vrip_intr_setmask2(vrip_chipset_tag_t, vrip_intr_handle_t,
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u_int32_t, int);
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void __vrip_intr_getstatus2(vrip_chipset_tag_t, vrip_intr_handle_t,
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u_int32_t*);
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void __vrip_register_cmu(vrip_chipset_tag_t, vrcmu_chipset_tag_t);
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void __vrip_register_gpio(vrip_chipset_tag_t, hpcio_chip_t);
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void __vrip_register_dmaau(vrip_chipset_tag_t, vrdmaau_chipset_tag_t);
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void __vrip_register_dcu(vrip_chipset_tag_t, vrdcu_chipset_tag_t);
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void __vrip_dump_level2mask(vrip_chipset_tag_t, void *);
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struct vrip_softc *the_vrip_sc = NULL;
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static const struct vrip_chipset_tag vrip_chipset_methods = {
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.vc_power = __vrip_power,
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.vc_intr_establish = __vrip_intr_establish,
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.vc_intr_disestablish = __vrip_intr_disestablish,
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.vc_intr_setmask1 = __vrip_intr_setmask1,
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.vc_intr_setmask2 = __vrip_intr_setmask2,
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.vc_intr_getstatus2 = __vrip_intr_getstatus2,
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.vc_register_cmu = __vrip_register_cmu,
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.vc_register_gpio = __vrip_register_gpio,
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.vc_register_dmaau = __vrip_register_dmaau,
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.vc_register_dcu = __vrip_register_dcu,
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};
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#ifdef SINGLE_VRIP_BASE
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CFATTACH_DECL(vrip, sizeof(struct vrip_softc),
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vripmatch, vripattach, NULL, NULL);
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static const struct vrip_unit vrip_units[] = {
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[VRIP_UNIT_PMU] = { "pmu",
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{ VRIP_INTR_POWER, VRIP_INTR_BAT, }, },
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[VRIP_UNIT_RTC] = { "rtc",
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{ VRIP_INTR_RTCL1, }, },
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[VRIP_UNIT_PIU] = { "piu",
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{ VRIP_INTR_PIU, },
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CMUMASK_PIU,
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ICUPIUINT_REG_W, MPIUINT_REG_W },
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[VRIP_UNIT_KIU] = { "kiu",
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{ VRIP_INTR_KIU, },
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CMUMASK_KIU,
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KIUINT_REG_W, MKIUINT_REG_W },
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[VRIP_UNIT_SIU] = { "siu",
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{ VRIP_INTR_SIU, }, },
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[VRIP_UNIT_GIU] = { "giu",
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{ VRIP_INTR_GIU, },
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0,
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GIUINT_L_REG_W,MGIUINT_L_REG_W,
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GIUINT_H_REG_W, MGIUINT_H_REG_W },
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[VRIP_UNIT_LED] = { "led",
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{ VRIP_INTR_LED, }, },
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[VRIP_UNIT_AIU] = { "aiu",
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{ VRIP_INTR_AIU, },
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CMUMASK_AIU,
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AIUINT_REG_W, MAIUINT_REG_W },
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[VRIP_UNIT_FIR] = { "fir",
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{ VRIP_INTR_FIR, },
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CMUMASK_FIR,
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FIRINT_REG_W, MFIRINT_REG_W },
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[VRIP_UNIT_DSIU]= { "dsiu",
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{ VRIP_INTR_DSIU, },
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CMUMASK_DSIU,
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DSIUINT_REG_W, MDSIUINT_REG_W },
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[VRIP_UNIT_PCIU]= { "pciu",
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{ VRIP_INTR_PCI, },
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CMUMASK_PCIU,
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PCIINT_REG_W, MPCIINT_REG_W },
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[VRIP_UNIT_SCU] = { "scu",
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{ VRIP_INTR_SCU, },
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0,
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SCUINT_REG_W, MSCUINT_REG_W },
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[VRIP_UNIT_CSI] = { "csi",
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{ VRIP_INTR_CSI, },
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CMUMASK_CSI,
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CSIINT_REG_W, MCSIINT_REG_W },
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[VRIP_UNIT_BCU] = { "bcu",
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{ VRIP_INTR_BCU, },
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0,
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BCUINT_REG_W, MBCUINT_REG_W },
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};
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void
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vripattach(struct device *parent, struct device *self, void *aux)
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{
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struct vrip_softc *sc = (struct vrip_softc*)self;
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printf("\n");
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sc->sc_units = vrip_units;
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sc->sc_nunits = sizeof(vrip_units)/sizeof(struct vrip_unit);
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sc->sc_icu_addr = VRIP_ICU_ADDR;
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sc->sc_sysint2 = SYSINT2_REG_W;
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sc->sc_msysint2 = MSYSINT2_REG_W;
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vripattach_common(parent, self, aux);
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}
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#endif /* SINGLE_VRIP_BASE */
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int
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vripmatch(struct device *parent, struct cfdata *match, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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#if defined(SINGLE_VRIP_BASE) && defined(TX39XX)
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if (!platid_match(&platid, &platid_mask_CPU_MIPS_VR_41XX))
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return (0);
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#endif /* SINGLE_VRIP_BASE && TX39XX */
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if (strcmp(ma->ma_name, match->cf_name))
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return (0);
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return (1);
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}
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void
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vripattach_common(struct device *parent, struct device *self, void *aux)
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{
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struct mainbus_attach_args *ma = aux;
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struct vrip_softc *sc = (struct vrip_softc*)self;
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sc->sc_chipset = vrip_chipset_methods; /* structure assignment */
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sc->sc_chipset.vc_sc = sc;
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#ifdef DIAGNOSTIC
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if (sc->sc_icu_addr == 0 ||
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sc->sc_sysint2 == 0 ||
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sc->sc_msysint2 == 0)
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panic("vripattach: missing register info.");
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#endif /* DIAGNOSTIC */
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/*
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* Map ICU (Interrupt Control Unit) register space.
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*/
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sc->sc_iot = ma->ma_iot;
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if (bus_space_map(sc->sc_iot, sc->sc_icu_addr,
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0x20 /*XXX lower area only*/,
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0, /* no flags */
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&sc->sc_ioh)) {
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printf("vripattach: can't map ICU register.\n");
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return;
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}
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/*
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* Disable all Level 1 interrupts.
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*/
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sc->sc_intrmask = 0;
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, MSYSINT1_REG_W, 0x0000);
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bus_space_write_2(sc->sc_iot, sc->sc_ioh, sc->sc_msysint2, 0x0000);
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/*
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* Level 1 interrupts are redirected to HwInt0
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*/
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vr_intr_establish(VR_INTR0, vrip_intr, self);
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the_vrip_sc = sc;
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/*
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* Attach each devices
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* GIU CMU DMAAU DCU interface interface is used by other system
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* device. so attach first
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*/
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sc->sc_pri = 2;
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config_search(vrip_search, self, vrip_print);
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/* Other system devices. */
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sc->sc_pri = 1;
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config_search(vrip_search, self, vrip_print);
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}
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int
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vrip_print(void *aux, const char *hoge)
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{
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struct vrip_attach_args *va = (struct vrip_attach_args*)aux;
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bus_addr_t endaddr, mask;
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if (va->va_addr != VRIPIFCF_ADDR_DEFAULT)
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aprint_normal(" addr 0x%08lx", va->va_addr);
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if (va->va_size != VRIPIFCF_SIZE_DEFAULT) {
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endaddr = (va->va_addr + va->va_size - 1);
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mask = ((va->va_addr ^ endaddr) & 0xff0000) ? 0xffffff:0xffff;
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aprint_normal("-%04lx", endaddr & mask);
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}
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if (va->va_addr2 != VRIPIFCF_ADDR2_DEFAULT)
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aprint_normal(", 0x%08lx", va->va_addr2);
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if (va->va_size2 != VRIPIFCF_SIZE2_DEFAULT)
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aprint_normal("-%04lx",
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(va->va_addr2 + va->va_size2 - 1) & 0xffff);
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return (UNCONF);
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}
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int
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vrip_search(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct vrip_softc *sc = (struct vrip_softc *)parent;
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struct vrip_attach_args va;
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platid_mask_t mask;
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if (cf->cf_loc[VRIPIFCF_PLATFORM] != VRIPIFCF_PLATFORM_DEFAULT) {
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mask = PLATID_DEREF(cf->cf_loc[VRIPIFCF_PLATFORM]);
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if (platid_match(&platid, &mask) == 0)
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return (0);
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}
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memset(&va, 0, sizeof(va));
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va.va_vc = &sc->sc_chipset;
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va.va_iot = sc->sc_iot;
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va.va_unit = cf->cf_loc[VRIPIFCF_UNIT];
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va.va_addr = cf->cf_loc[VRIPIFCF_ADDR];
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va.va_size = cf->cf_loc[VRIPIFCF_SIZE];
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va.va_addr2 = cf->cf_loc[VRIPIFCF_ADDR2];
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va.va_size2 = cf->cf_loc[VRIPIFCF_SIZE2];
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va.va_gpio_chips = sc->sc_gpio_chips;
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va.va_cc = sc->sc_chipset.vc_cc;
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va.va_ac = sc->sc_chipset.vc_ac;
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va.va_dc = sc->sc_chipset.vc_dc;
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if ((config_match(parent, cf, &va) == sc->sc_pri))
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config_attach(parent, cf, &va, vrip_print);
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return (0);
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}
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int
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__vrip_power(vrip_chipset_tag_t vc, int unit, int onoff)
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{
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struct vrip_softc *sc = vc->vc_sc;
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const struct vrip_unit *vu;
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if (sc->sc_chipset.vc_cc == NULL)
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return (0); /* You have no clock mask unit yet. */
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if (!VALID_UNIT(sc, unit))
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return (0);
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vu = &sc->sc_units[unit];
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return (*sc->sc_chipset.vc_cc->cc_clock)(sc->sc_chipset.vc_cc,
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vu->vu_clkmask, onoff);
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}
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vrip_intr_handle_t
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__vrip_intr_establish(vrip_chipset_tag_t vc, int unit, int line, int level,
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int (*ih_fun)(void *), void *ih_arg)
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{
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struct vrip_softc *sc = vc->vc_sc;
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const struct vrip_unit *vu;
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struct intrhand *ih;
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if (!VALID_UNIT(sc, unit))
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return (NULL);
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vu = &sc->sc_units[unit];
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ih = &sc->sc_intrhands[vu->vu_intr[line]];
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if (ih->ih_fun) /* Can't share level 1 interrupt */
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return (NULL);
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ih->ih_fun = ih_fun;
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ih->ih_arg = ih_arg;
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ih->ih_unit = vu;
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/* Mask level 2 interrupt mask register. (disable interrupt) */
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vrip_intr_setmask2(vc, ih, ~0, 0);
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/* Unmask Level 1 interrupt mask register (enable interrupt) */
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vrip_intr_setmask1(vc, ih, 1);
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return ((void *)ih);
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}
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void
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__vrip_intr_disestablish(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
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{
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struct intrhand *ih = handle;
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ih->ih_fun = NULL;
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ih->ih_arg = NULL;
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/* Mask level 2 interrupt mask register(if any). (disable interrupt) */
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vrip_intr_setmask2(vc, ih, ~0, 0);
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/* Mask Level 1 interrupt mask register (disable interrupt) */
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vrip_intr_setmask1(vc, ih, 0);
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}
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void
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vrip_intr_suspend()
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{
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struct vrip_softc *sc = the_vrip_sc;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, (1<<VRIP_INTR_POWER));
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bus_space_write_2 (iot, ioh, sc->sc_msysint2, 0);
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}
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void
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vrip_intr_resume()
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{
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struct vrip_softc *sc = the_vrip_sc;
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u_int32_t reg = sc->sc_intrmask;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
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bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);
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}
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/* Set level 1 interrupt mask. */
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void
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__vrip_intr_setmask1(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
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int enable)
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{
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struct vrip_softc *sc = vc->vc_sc;
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struct intrhand *ih = handle;
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int level1 = ih - sc->sc_intrhands;
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bus_space_tag_t iot = sc->sc_iot;
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bus_space_handle_t ioh = sc->sc_ioh;
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u_int32_t reg = sc->sc_intrmask;
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DPRINTF(("__vrip_intr_setmask1: SYSINT: %s %d\n",
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enable ? "enable" : "disable", level1));
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reg = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
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((bus_space_read_2 (iot, ioh, sc->sc_msysint2) << 16)&0xffff0000);
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if (enable)
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reg |= (1 << level1);
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else {
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reg &= ~(1 << level1);
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}
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sc->sc_intrmask = reg;
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bus_space_write_2 (iot, ioh, MSYSINT1_REG_W, reg & 0xffff);
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bus_space_write_2 (iot, ioh, sc->sc_msysint2, (reg >> 16) & 0xffff);
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DBG_BIT_PRINT(reg);
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return;
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}
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void
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__vrip_dump_level2mask(vrip_chipset_tag_t vc, vrip_intr_handle_t handle)
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{
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struct vrip_softc *sc = vc->vc_sc;
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struct intrhand *ih = handle;
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const struct vrip_unit *vu = ih->ih_unit;
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u_int32_t reg;
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if (vu->vu_mlreg) {
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DPRINTF(("level1[%d] level2 mask:", vu->vu_intr[0]));
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reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);
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if (vu->vu_mhreg) { /* GIU [16:31] case only */
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reg |= (bus_space_read_2(sc->sc_iot, sc->sc_ioh,
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vu->vu_mhreg) << 16);
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dbg_bit_print(reg);
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} else
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dbg_bit_print(reg);
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}
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}
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/* Get level 2 interrupt status */
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void
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__vrip_intr_getstatus2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
|
|
u_int32_t *mask /* Level 2 mask */)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
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|
struct intrhand *ih = handle;
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|
const struct vrip_unit *vu = ih->ih_unit;
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|
u_int32_t reg;
|
|
|
|
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
|
|
vu->vu_lreg);
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|
reg |= ((bus_space_read_2(sc->sc_iot, sc->sc_ioh,
|
|
vu->vu_hreg) << 16)&0xffff0000);
|
|
/* dbg_bit_print(reg);*/
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|
*mask = reg;
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|
}
|
|
|
|
/* Set level 2 interrupt mask. */
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|
void
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|
__vrip_intr_setmask2(vrip_chipset_tag_t vc, vrip_intr_handle_t handle,
|
|
u_int32_t mask /* Level 2 mask */, int onoff)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
|
|
struct intrhand *ih = handle;
|
|
const struct vrip_unit *vu = ih->ih_unit;
|
|
u_int16_t reg;
|
|
|
|
DPRINTF(("vrip_intr_setmask2:\n"));
|
|
DUMP_LEVEL2MASK(vc, handle);
|
|
#ifdef WINCE_DEFAULT_SETTING
|
|
#warning WINCE_DEFAULT_SETTING
|
|
#else
|
|
if (vu->vu_mlreg) {
|
|
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg);
|
|
if (onoff)
|
|
reg |= (mask&0xffff);
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|
else
|
|
reg &= ~(mask&0xffff);
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh, vu->vu_mlreg, reg);
|
|
if (vu->vu_mhreg != 0) { /* GIU [16:31] case only */
|
|
reg = bus_space_read_2(sc->sc_iot, sc->sc_ioh,
|
|
vu->vu_mhreg);
|
|
if (onoff)
|
|
reg |= ((mask >> 16) & 0xffff);
|
|
else
|
|
reg &= ~((mask >> 16) & 0xffff);
|
|
bus_space_write_2(sc->sc_iot, sc->sc_ioh,
|
|
vu->vu_mhreg, reg);
|
|
}
|
|
}
|
|
#endif /* WINCE_DEFAULT_SETTING */
|
|
DUMP_LEVEL2MASK(vc, handle);
|
|
|
|
return;
|
|
}
|
|
|
|
int
|
|
vrip_intr(void *arg, u_int32_t pc, u_int32_t statusReg)
|
|
{
|
|
struct vrip_softc *sc = (struct vrip_softc*)arg;
|
|
bus_space_tag_t iot = sc->sc_iot;
|
|
bus_space_handle_t ioh = sc->sc_ioh;
|
|
int i;
|
|
u_int32_t reg, mask;
|
|
/*
|
|
* Read level1 interrupt status.
|
|
*/
|
|
reg = (bus_space_read_2 (iot, ioh, SYSINT1_REG_W)&0xffff) |
|
|
((bus_space_read_2 (iot, ioh, sc->sc_sysint2)<< 16)&0xffff0000);
|
|
mask = (bus_space_read_2 (iot, ioh, MSYSINT1_REG_W)&0xffff) |
|
|
((bus_space_read_2 (iot, ioh, sc->sc_msysint2)<< 16)&0xffff0000);
|
|
reg &= mask;
|
|
|
|
/*
|
|
* Dispatch each handler.
|
|
*/
|
|
for (i = 0; i < 32; i++) {
|
|
register struct intrhand *ih = &sc->sc_intrhands[i];
|
|
if (ih->ih_fun && (reg & (1 << i))) {
|
|
ih->ih_fun(ih->ih_arg);
|
|
}
|
|
}
|
|
|
|
return (1);
|
|
}
|
|
|
|
void
|
|
__vrip_register_cmu(vrip_chipset_tag_t vc, vrcmu_chipset_tag_t cmu)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
|
|
|
|
sc->sc_chipset.vc_cc = cmu;
|
|
}
|
|
|
|
void
|
|
__vrip_register_gpio(vrip_chipset_tag_t vc, hpcio_chip_t chip)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
|
|
|
|
if (chip->hc_chipid < 0 || VRIP_NIOCHIPS <= chip->hc_chipid)
|
|
panic("%s: '%s' has unknown id, %d", __FUNCTION__,
|
|
chip->hc_name, chip->hc_chipid);
|
|
sc->sc_gpio_chips[chip->hc_chipid] = chip;
|
|
}
|
|
|
|
void
|
|
__vrip_register_dmaau(vrip_chipset_tag_t vc, vrdmaau_chipset_tag_t dmaau)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
|
|
|
|
sc->sc_chipset.vc_ac = dmaau;
|
|
}
|
|
|
|
void
|
|
__vrip_register_dcu(vrip_chipset_tag_t vc, vrdcu_chipset_tag_t dcu)
|
|
{
|
|
struct vrip_softc *sc = vc->vc_sc;
|
|
|
|
sc->sc_chipset.vc_dc = dcu;
|
|
}
|