625 lines
15 KiB
ArmAsm
625 lines
15 KiB
ArmAsm
/* $NetBSD: locore.S,v 1.2 2001/06/24 01:15:41 simonb Exp $ */
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/* $OpenBSD: locore.S,v 1.4 1997/01/26 09:06:38 rahnds Exp $ */
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/*
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* Copyright 2001 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Eduardo Horvath and Simon Burge for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#undef NOCACHE
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#include "opt_ddb.h"
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#include "fs_kernfs.h"
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#include "opt_ipkdb.h"
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#include "opt_lockdebug.h"
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#include "opt_multiprocessor.h"
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#include "opt_ppcarch.h"
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#include "assym.h"
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#include <sys/syscall.h>
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#include <machine/param.h>
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/asm.h>
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#include <powerpc/spr.h>
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#include <powerpc/ibm4xx/dcr.h>
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#include <powerpc/ibm4xx/pmap.h>
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/*
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* Some instructions gas doesn't understand (yet?)
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*/
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#define bdneq bdnzf 2,
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#define INTSTK (8*1024) /* 8K interrupt stack */
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#define SPILLSTK 1024 /* 1K spill stack */
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/*
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* Globals
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*/
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GLOBAL(startsym)
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.long 0 /* start symbol table */
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GLOBAL(endsym)
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.long 0 /* end symbol table */
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GLOBAL(proc0paddr)
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.long 0 /* proc0 p_addr */
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GLOBAL(intrnames)
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.asciz "clock", "irq1", "irq2", "irq3"
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.asciz "irq4", "irq5", "irq6", "irq7"
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.asciz "irq8", "irq9", "irq10", "irq11"
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.asciz "irq12", "irq13", "irq14", "irq15"
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.asciz "irq16", "irq17", "irq18", "irq19"
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.asciz "irq20", "irq21", "irq22", "irq23"
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.asciz "irq24", "irq25", "irq26", "irq27"
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.asciz "irq28", "softnet", "softclock", "softserial"
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.asciz "statclock"
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GLOBAL(eintrnames)
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.align 4
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GLOBAL(intrcnt)
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.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.long 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0
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.long 0
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GLOBAL(eintrcnt)
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GLOBAL(powersave)
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.long 0
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/*
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* File-scope for locore.S
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*/
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.data
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idle_u:
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.long 0 /* fake uarea during idle after exit */
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/*
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* This symbol is here for the benefit of kvm_mkdb, and is supposed to
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* mark the start of kernel text.
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*/
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.text
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.globl _C_LABEL(kernel_text)
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_C_LABEL(kernel_text):
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/*
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* Startup entry. Note, this must be the first thing in the text
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* segment!
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*/
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.text
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.globl __start
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__start:
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b 1f
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/* Reserve some space for info_block required for IBM eval board bootloader */
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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1:
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mr 31,3 /* Save address of PROM info_block */
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li 0,0
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mtmsr 0 /* Disable FPU/MMU/exceptions */
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isync
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/* PPC405GP errata, item #58.
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* Load string instructions may write incorrect data into the last GPR
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* targeted in the operation.
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* Workaround: set OCM0_DSCNTL[DSEN]=0 and OCM0_DSCNTL[DOF]=0 */
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mtdcr DCR_OCM0_DSCNTL, 0 /* Disable Data access to OCM */
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mtdcr DCR_OCM0_ISCNTL, 0 /* Disable Instruction access to OCM. Just in case */
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/*
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* Cpu detect.
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*
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*/
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__start_cpu0:
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#ifdef NOCACHE
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/* Disable all caches for physical addresses */
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li 0,0
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#else
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/* Allow cacheing for only the first 2GB of RAM */
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lis 0,0xffff
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#endif
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mtdccr 0
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mticcr 0
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/* Invalidate all TLB entries */
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tlbia
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sync
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isync
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/* compute end of kernel memory */
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lis 8,_C_LABEL(end)@ha
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addi 8,8,_C_LABEL(end)@l
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#if defined(DDB) || defined(KERNFS)
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/* If we had symbol table location we'd store it here and would've adjusted r8 here */
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lis 7,_C_LABEL(startsym)@ha
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addi 7,7,_C_LABEL(startsym)@l
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stw 8,0(7)
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lis 7,_C_LABEL(endsym)@ha
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addi 7,7,_C_LABEL(endsym)@l
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stw 8,0(7)
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#endif
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/*
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* Set up TLB entry to cover kernel addresses.
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*
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* XXX: Skip TLB 0 for now, due to unresolved TLB 0 replacement
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* and hard hangs
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*/
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li 0,1
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mtpid 0
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sync
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li 0,0
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#ifdef NOCACHE
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li 4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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li 4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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li 3,TLB_VALID|TLB_PG_16M
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tlbwe 4,0,1 /* Load the data(Low) portion of the entry */
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tlbwe 3,0,0 /* Load the tag(High) portion of the entry */
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#if 1
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/* Damn. Have to be able to access all real memory.... Hardcode for 32M for now. */
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li 0,1
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lis 4,0x01000000@h
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ori 3,4,0
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#ifdef NOCACHE
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addi 4,4,TLB_EX|TLB_WR|TLB_I /* |TLB_W */
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#else
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addi 4,4,TLB_EX|TLB_WR /* |TLB_W */
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#endif
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addi 3,3,TLB_VALID|TLB_PG_16M
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tlbwe 4,0,1 /* Load the data(Low) portion of the entry */
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tlbwe 3,0,0 /* Load the tag(High) portion of the entry */
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#endif
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/* set up a TLB mapping to cover uart0 */
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lis 3,0xef000000@h /* Load the virtual address */
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ori 4,3,0 /* Load the physical address */
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clrrwi 4,4,10 /* Mask off the real page number */
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/* write, execute, cache inhibit, guarded */
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ori 4,4,(TLB_WR|TLB_EX|TLB_I|TLB_G)
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clrrwi 3,3,10 /* Mask off the effective page number */
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ori 3,3,(TLB_VALID|TLB_PG_16M)
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li 0,2
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tlbwe 4,0,1 /* Load the data portion of the entry */
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tlbwe 3,0,0 /* Load the tag portion of the entry */
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/* END of TLB setup */
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li 9,PGOFSET
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add 8,8,9
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andc 8,8,9
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addi 8,8,NBPG
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lis 9,idle_u@ha
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stw 8,idle_u@l(9)
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addi 8,8,USPACE /* space for idle_u */
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lis 9,_C_LABEL(proc0paddr)@ha
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stw 8,_C_LABEL(proc0paddr)@l(9)
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addi 1,8,USPACE-FRAMELEN /* stackpointer for proc0 */
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mr 4,1 /* end of mem reserved for kernel */
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xor 0,0,0
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stwu 0,-16(1) /* end of stack chain */
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lis 3,__start@ha
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addi 3,3,__start@l
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mr 6,31 /* info_block address */
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bl _C_LABEL(initppc)
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bl _C_LABEL(main)
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loop: b loop /* XXX not reached */
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/*
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* No processes are runnable, so loop waiting for one.
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* Separate label here for accounting purposes.
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* When we get here, interrupts are off (MSR[EE]=0) and sched_lock is held.
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*/
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ASENTRY(Idle)
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lis 8,_C_LABEL(sched_whichqs)@ha
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lwz 9,_C_LABEL(sched_whichqs)@l(8)
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or. 9,9,9
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bne- .Lsw1 /* at least one queue non-empty */
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wrteei 1 /* reenable ints again */
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/* May do some power saving here? */
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/* Check if we can use power saving mode */
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lis 8,_C_LABEL(powersave)@ha
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lwz 9,_C_LABEL(powersave)@l(8)
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or. 9,9,9
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beq 1f
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/* TODO: Enter power saving mode here */
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1:
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wrteei 0 /* disable interrupts while manipulating runque */
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b _ASM_LABEL(Idle)
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/*
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* switchexit gets called from cpu_exit to complete the exit procedure.
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*/
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ENTRY(switchexit)
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/* First switch to the idle pcb/kernel stack */
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lis 6,idle_u@ha
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lwz 6,idle_u@l(6)
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lis 7,_C_LABEL(curpcb)@ha
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stw 6,_C_LABEL(curpcb)@l(7)
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addi 1,6,USPACE-16 /* 16 bytes are reserved at stack top */
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/*
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* Schedule the vmspace and stack to be freed (the proc arg is
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* already in r3).
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*/
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bl _C_LABEL(exit2)
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/* Fall through to cpu_switch to actually select another proc */
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li 3,0 /* indicate exited process */
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/*
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* void cpu_switch(struct proc *p)
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* Find a runnable process and switch to it.
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*/
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/* XXX noprofile? --thorpej@netbsd.org */
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ENTRY(cpu_switch)
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mflr 0 /* save lr */
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stw 0,4(1)
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stwu 1,-16(1)
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stw 31,12(1)
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stw 30,8(1)
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mr 30,3
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lis 3,_C_LABEL(curproc)@ha
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xor 31,31,31
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stw 31,_C_LABEL(curproc)@l(3) /* Zero to not accumulate cpu time */
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lis 3,_C_LABEL(curpcb)@ha
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lwz 31,_C_LABEL(curpcb)@l(3)
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xor 3,3,3
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bl _C_LABEL(lcsplx)
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stw 3,PCB_SPL(31) /* save spl */
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wrteei 0 /* disable interrupts while manipulating runque */
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/* Find a new process */
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lis 8,_C_LABEL(sched_whichqs)@ha
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lwz 9,_C_LABEL(sched_whichqs)@l(8)
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or. 9,9,9
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beq- _ASM_LABEL(Idle) /* all queues empty */
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.Lsw1:
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cntlzw 10,9
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lis 4,_C_LABEL(sched_qs)@ha
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addi 4,4,_C_LABEL(sched_qs)@l
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slwi 3,10,3
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add 3,3,4 /* select queue */
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lwz 31,P_FORW(3) /* unlink first proc from queue */
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lwz 4,P_FORW(31)
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stw 4,P_FORW(3)
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stw 3,P_BACK(4)
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cmpl 0,3,4 /* queue empty? */
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bne 1f
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lis 3,0x80000000@h
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srw 3,3,10
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andc 9,9,3
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stw 9,_C_LABEL(sched_whichqs)@l(8) /* mark it empty */
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1:
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/* just did this resched thing */
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xor 3,3,3
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lis 4,_C_LABEL(want_resched)@ha
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stw 3,_C_LABEL(want_resched)@l(4)
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stw 3,P_BACK(31) /* probably superfluous */
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/* Process now running on a processor. */
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li 3,SONPROC /* p->p_stat = SONPROC */
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stb 3,P_STAT(31)
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/* record new process */
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lis 4,_C_LABEL(curproc)@ha
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stw 31,_C_LABEL(curproc)@l(4)
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wrteei 1 /* Now we can interrupt again */
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cmpl 0,31,30 /* is it the same process? */
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beq switch_return
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or. 30,30,30 /* old process was exiting? */
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beq switch_exited
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#ifndef PPC_IBM4XX
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mfsr 10,USER_SR /* save USER_SR for copyin/copyout */
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#else
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li 10,0 /* no SR for 4xx CPUs */
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#endif
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mfcr 11 /* save cr */
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mr 12,2 /* save r2 */
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stwu 1,-SFRAMELEN(1) /* still running on old stack */
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stmw 10,8(1)
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lwz 3,P_ADDR(30)
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stw 1,PCB_SP(3) /* save SP */
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switch_exited:
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wrteei 0 /* disable interrupts while actually switching */
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/* indicate new pcb */
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lwz 4,P_ADDR(31)
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lis 5,_C_LABEL(curpcb)@ha
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stw 4,_C_LABEL(curpcb)@l(5)
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/* save real pmap pointer for spill fill */
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lwz 5,PCB_PMR(4)
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lis 6,_C_LABEL(curpm)@ha
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stwu 5,_C_LABEL(curpm)@l(6)
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stwcx. 5,0,6 /* clear possible reservation */
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/* Switch to the new virtual space */
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/* Do not have to do anything here. TLB PID gets updated on return from trap. */
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lwz 1,PCB_SP(4) /* get new procs SP */
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wrteei 1 /* interrupts are okay again */
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lmw 10,8(1) /* get other regs */
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lwz 1,0(1) /* get saved SP */
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mr 2,12 /* get saved r2 */
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mtcr 11 /* get saved cr */
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isync
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switch_return:
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mr 30,7 /* save proc pointer */
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lwz 3,PCB_SPL(4)
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bl _C_LABEL(lcsplx)
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0:
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lis 3,_C_LABEL(curpm)@ha
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addi 3,3,_C_LABEL(curpm)@l /* Do we need a context? */
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lwz 4,PM_CTX(3)
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cmpwi 4,0
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# mtspr SPR_SPR0,4 /* Always keep the current ctx here */
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mr 3,30
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bne 1f
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bl _C_LABEL(ctx_alloc)
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mr 3,30 /* get curproc for special fork
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returns */
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b 0b /* Reload */
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1:
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lwz 31,12(1)
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lwz 30,8(1)
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addi 1,1,16
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lwz 0,4(1)
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mtlr 0
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blr
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/*
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* Child comes here at the end of a fork.
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* Return to userspace via the trap return path.
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*/
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.globl _C_LABEL(fork_trampoline)
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_C_LABEL(fork_trampoline):
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xor 3,3,3
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bl _C_LABEL(lcsplx)
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mtlr 31
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mr 3,30
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blrl /* jump indirect to r31 */
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b trapexit
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/*
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* Pull in common trap vector code.
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*/
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#include <powerpc/ibm4xx/trap_subr.S>
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#include <powerpc/ibm4xx/4xx_trap_subr.S>
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/*
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* int setfault()
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*
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* Similar to setjmp to setup for handling faults on accesses to user memory.
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* Any routine using this may only call bcopy, either the form below,
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* or the (currently used) C code optimized, so it doesn't use any non-volatile
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* registers.
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*/
|
|
.globl _C_LABEL(setfault)
|
|
_C_LABEL(setfault):
|
|
mflr 0
|
|
mfcr 12
|
|
lis 4,_C_LABEL(curpcb)@ha
|
|
lwz 4,_C_LABEL(curpcb)@l(4)
|
|
stw 3,PCB_FAULT(4)
|
|
stw 0,0(3)
|
|
stw 1,4(3)
|
|
stw 2,8(3)
|
|
stmw 12,12(3)
|
|
xor 3,3,3
|
|
blr
|
|
|
|
.globl _C_LABEL(enable_intr)
|
|
_C_LABEL(enable_intr):
|
|
wrteei 1
|
|
blr
|
|
|
|
.globl _C_LABEL(disable_intr)
|
|
_C_LABEL(disable_intr):
|
|
wrteei 0
|
|
blr
|
|
|
|
.globl _C_LABEL(ppc4xx_reset)
|
|
_C_LABEL(ppc4xx_reset):
|
|
mfspr 3,SPR_DBCR0
|
|
oris 3,r13,DBCR0_RST_SYSTEM@h
|
|
mtspr SPR_DBCR0,3
|
|
ba 0
|
|
|
|
#if 0
|
|
/*
|
|
* XXXX the following doesn't quite work right yet.
|
|
*/
|
|
/*
|
|
* void bcopy(const void *src, void *dst, size_t len);
|
|
*
|
|
* swap r3 and r4 and fall through to memcopy.
|
|
*/
|
|
.globl _C_LABEL(bcopy)
|
|
_C_LABEL(bcopy):
|
|
mr r0,r3
|
|
mr r3,r4
|
|
mr r4,r0
|
|
/* FALLTHROUGH */
|
|
|
|
/*
|
|
* void * memcpy(void *dst (r3), const void *src (r4), size_t len (r5));
|
|
*
|
|
* Copy memory (obviously)
|
|
*
|
|
* We will try to do data cache block aligned stores so we
|
|
* can use block allocate and not have to read from the
|
|
* destination.
|
|
*
|
|
* Register use:
|
|
*
|
|
* r1 stack (of course)
|
|
* r3 dst
|
|
* r4 src
|
|
* r5 len
|
|
* r6 tmp
|
|
* r7 holds 32
|
|
* r8 holds dst
|
|
* r24-r31 block move regs
|
|
*
|
|
*/
|
|
|
|
ENTRY(memcpy)
|
|
stwu r1,-(10*4)(r1) /* Allocate some RAM to save 8 regs to. */
|
|
cmpwi r5, 32 /* Less than 32 bytes ? */
|
|
stmw r24,8(r1) /* Save ALL regs (could be optimized) */
|
|
|
|
mr r8,r3 /* save dst */
|
|
li r7,32
|
|
|
|
dcbt 0,r4 /* Start bringing in cache line. */
|
|
blt 1f /* Finish up */
|
|
|
|
neg r6,r3 /* Find how far unaligned we are... */
|
|
andi. r6,r6,31 /* Cache-align dest. */
|
|
mtxer r6
|
|
sub r5,r5,r6 /* subtract count */
|
|
lswx r24,0,r4 /* Load some. */
|
|
add r4,r4,r6
|
|
dcbt 0,r4 /* Fetch next line */
|
|
stswx r24,0,r3 /* Store some */
|
|
add r3,r3,r6
|
|
addic. r6,r5,-32 /* Pre-decrement next line */
|
|
ble 1f /* Less than 32-bytes? finishup */
|
|
|
|
/* Dest should not be cache line aligned. */
|
|
/* XXX need gas 2.11 to grok dcba insn */
|
|
#ifdef GAS_2_11
|
|
dcba 0,r3 /* Allocate a line */
|
|
#else
|
|
.long 0x7c001dec /* dcba 0,r3 */
|
|
#endif
|
|
0:
|
|
dcbt r7,r4 /* Bring in the next line, too */
|
|
|
|
lswi r24,r4,32
|
|
addi r4,r4,32 /* Inc src */
|
|
mr r5,r6
|
|
|
|
addic. r6,r5,-32
|
|
stswi r24,r3,32
|
|
addi r3,r3,32 /* Inc dst */
|
|
#ifdef GAS_2_11
|
|
dcba 0,r3 /* Allocate another line */
|
|
#else
|
|
.long 0x7c071dec /* dcba r7,r3 */
|
|
#endif bgt 0b
|
|
1:
|
|
mtxer r5 /* Store byte count */
|
|
lswx r24,0,r4 /* Load up to 32 bytes */
|
|
stswx r24,0,r3 /* Store up to 32 bytes */
|
|
|
|
mr r3,r8 /* Return dst */
|
|
|
|
lmw r24,8(r1)
|
|
addi r1,r1,(10*4)
|
|
blr
|
|
#endif
|