351 lines
13 KiB
C
351 lines
13 KiB
C
/* $NetBSD: elan520reg.h,v 1.10 2008/04/28 20:23:24 martin Exp $ */
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/*-
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* Copyright (c) 2002 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Register definitions for the AMD Elan SC520 System Controller.
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*/
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#ifndef _I386_PCI_ELAN520REG_H_
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#define _I386_PCI_ELAN520REG_H_
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#include <sys/cdefs.h>
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#define MMCR_BASE_ADDR 0xfffef000
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/*
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* Am5x86 CPU Registers.
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*/
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#define MMCR_REVID 0x0000
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#define MMCR_CPUCTL 0x0002
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#define REVID_PRODID 0xff00 /* product ID */
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#define REVID_PRODID_SHIFT 8
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#define REVID_MAJSTEP 0x00f0 /* stepping major */
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#define REVID_MAJSTEP_SHIFT 4
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#define REVID_MINSTEP 0x000f /* stepping minor */
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#define PRODID_ELAN_SC520 0x00 /* Elan SC520 */
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#define CPUCTL_CPU_CLK_SPD_MASK 0x03 /* CPU clock speed */
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#define CPUCTL_CACHE_WR_MODE 0x10 /* cache mode (0 = wb, 1 = wt) */
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/*
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* Performance Registers
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*/
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#define MMCR_DBCTL 0x0040 /* SDRAM Buffer Control */
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#define MMCR_DBCTL_RAB_ENB __BIT(4) /* enable read-ahead */
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#define MMCR_DBCTL_WB_WM_MASK __BITS(3,2) /* write buffer watermark */
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#define MMCR_DBCTL_WB_WM_28DW __SHIFTIN(0, MMCR_DBCTL_WB_WM_MASK)
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#define MMCR_DBCTL_WB_WM_24DW __SHIFTIN(1, MMCR_DBCTL_WB_WM_MASK)
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#define MMCR_DBCTL_WB_WM_16DW __SHIFTIN(2, MMCR_DBCTL_WB_WM_MASK)
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#define MMCR_DBCTL_WB_WM_8DW __SHIFTIN(3, MMCR_DBCTL_WB_WM_MASK)
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#define MMCR_DBCTL_WB_FLUSH __BIT(1) /* write 1 to flush wr buf */
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#define MMCR_DBCTL_WB_ENB __BIT(0) /* enable write buffer */
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#define MMCR_HBCTL 0x0060 /* Host Bridge Control */
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#define MMCR_HBCTL_PCI_RST __BIT(15)
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#define MMCR_HBCTL_T_PURGE_RD_ENB __BIT(10)
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#define MMCR_HBCTL_T_DLYTR_ENB_MASK __BITS(9,8)
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#define MMCR_HBCTL_T_DLYTR_ENB_WAIT \
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__SHIFTIN(0, MMCR_HBCTL_T_DLYTR_ENB_MASK)
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#define MMCR_HBCTL_T_DLYTR_ENB_AUTORETRY\
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__SHIFTIN(1, MMCR_HBCTL_T_DLYTR_ENB_MASK)
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#define MMCR_HBCTL_T_DLYTR_ENB_RSVD0 \
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__SHIFTIN(2, MMCR_HBCTL_T_DLYTR_ENB_MASK)
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#define MMCR_HBCTL_T_DLYTR_ENB_RSVD1 \
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__SHIFTIN(3, MMCR_HBCTL_T_DLYTR_ENB_MASK)
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#define MMCR_HBCTL_M_WPOST_ENB __BIT(3)
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#define MMCR_SYSARBCTL 0x0070 /* System Arbiter Control */
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#define MMCR_SYSARBCTL_CNCR_MODE_ENB __BIT(1)
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#define MMCR_SYSARBCTL_GNT_TO_INT_ENB __BIT(0) /* 1: interrupt when the
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* PCI bus arbiter
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* detects a time-out
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*/
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#define MMCR_PCIARBSTA 0x71 /* PCI Bus Arbiter Status */
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#define MMCR_PCIARBSTA_GNT_TO_STA __BIT(7)
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#define MMCR_PCIARBSTA_GNT_TO_ID __BITS(3, 0)
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/*
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* PCI Host Bridge Registers
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*/
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#define MMCR_HBMSTIRQCTL 0x66 /* Host Bridge Master Interrupt Ctrl */
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#define MMCR_HBMSTIRQCTL_RSVD0 __BITS(15, 14)
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/* Interrupt Selects
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*
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* 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
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* 1: generate NMI
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*/
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/* Master Retry Time-Out */
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#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_SEL __BIT(13)
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/* Master Target Abort */
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#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_SEL __BIT(12)
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/* Master Abort */
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#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_SEL __BIT(11)
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/* Master System Error */
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#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_SEL __BIT(10)
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/* Master Received PERR */
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#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_SEL __BIT(9)
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/* Master Detected PERR */
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#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_SEL __BIT(8)
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#define MMCR_HBMSTIRQCTL_RSVD1 __BITS(7, 6)
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/* Interrupt Enables */
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/* Master Retry Time-Out */
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#define MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB __BIT(5)
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/* Master Target Abort */
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#define MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB __BIT(4)
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/* Master Abort */
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#define MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB __BIT(3)
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/* Master System Error */
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#define MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB __BIT(2)
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/* Master Received PERR */
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#define MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB __BIT(1)
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/* Master Detected PERR */
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#define MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB __BIT(0)
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/* Host Bridge Target Interrupt Ctrl. 16 bits. */
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#define MMCR_HBTGTIRQCTL 0x62
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#define MMCR_HBTGTIRQCTL_RSVD0 __BITS(15, 11)
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/* Interrupt Selects
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*
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* 0: generate maskable interrupt (see MMCR_PCIHOSTMAP)
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* 1: generate NMI
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*/
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#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_SEL __BIT(10)
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#define MMCR_HBTGTIRQCTL_T_APER_IRQ_SEL __BIT(9)
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#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_SEL __BIT(8)
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#define MMCR_HBTGTIRQCTL_RSVD1 __BITS(7, 3)
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/* Interrupt Enables */
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/* Target Delayed Transaction Time-out */
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#define MMCR_HBTGTIRQCTL_T_DLYTO_IRQ_ENB __BIT(2)
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/* Target Address Parity */
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#define MMCR_HBTGTIRQCTL_T_APER_IRQ_ENB __BIT(1)
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/* Target Data Parity */
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#define MMCR_HBTGTIRQCTL_T_DPER_IRQ_ENB __BIT(0)
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/* Host Bridge Master Interrupt Status. 16 bits. */
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#define MMCR_HBMSTIRQSTA 0x68
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/* Host Bridge Master Interrupt Address */
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#define MMCR_MSTINTADD 0x6c
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#define MMCR_HBMSTIRQSTA_RSVD0 __BITS(15, 12)
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#define MMCR_HBMSTIRQSTA_M_CMD_IRQ_ID __BITS(11, 8)
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#define MMCR_HBMSTIRQSTA_RSVD1 __BITS(7, 6)
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#define MMCR_HBMSTIRQSTA_M_RTRTO_IRQ_STA __BIT(5)
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#define MMCR_HBMSTIRQSTA_M_TABRT_IRQ_STA __BIT(4)
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#define MMCR_HBMSTIRQSTA_M_MABRT_IRQ_STA __BIT(3)
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#define MMCR_HBMSTIRQSTA_M_SERR_IRQ_STA __BIT(2)
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#define MMCR_HBMSTIRQSTA_M_RPER_IRQ_STA __BIT(1)
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#define MMCR_HBMSTIRQSTA_M_DPER_IRQ_STA __BIT(0)
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/* The PCI master interrupts that NetBSD is interested in. */
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#define MMCR_MSTIRQ_ACT (MMCR_HBMSTIRQCTL_M_RTRTO_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_TABRT_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_MABRT_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_SERR_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_RPER_IRQ_ENB |\
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MMCR_HBMSTIRQCTL_M_DPER_IRQ_ENB)
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/* Host Bridge Target Interrupt Status. 16 bits. */
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#define MMCR_HBTGTIRQSTA 0x64
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#define MMCR_HBTGTIRQSTA_RSVD0 __BITS(15, 12)
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/* Target Interrupt Identification */
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#define MMCR_HBTGTIRQSTA_T_IRQ_ID __BITS(11, 8)
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#define MMCR_HBTGTIRQSTA_RSVD1 __BITS(7, 3)
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/* Status bits. Write 1 to clear. */
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#define MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA __BIT(2)
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#define MMCR_HBTGTIRQSTA_T_APER_IRQ_STA __BIT(1)
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#define MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA __BIT(0)
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/* The PCI target interrupts that NetBSD is interested in. */
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#define MMCR_TGTIRQ_ACT (MMCR_HBTGTIRQSTA_T_DLYTO_IRQ_STA |\
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MMCR_HBTGTIRQSTA_T_APER_IRQ_STA |\
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MMCR_HBTGTIRQSTA_T_DPER_IRQ_STA)
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#define MMCR_PCIHOSTMAP 0x0d14 /* PCI Host Bridge Interrupt Mapping */
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#define MMCR_PCIHOSTMAP_PCI_NMI_ENB __BIT(8)
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#define MMCR_PCIHOSTMAP_PCI_IRQ_MAP __BITS(4, 0)
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/* Programmable Interrupt Controller. 8 bits. */
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#define MMCR_PICICR 0xd00
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#define MMCR_PICICR_NMI_DONE __BIT(7)
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#define MMCR_PICICR_NMI_ENB __BIT(6)
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#define MMCR_PICICR_RSVD0 __BITS(5, 3)
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#define MMCR_PICICR_S2_GINT_MODE __BIT(2)
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#define MMCR_PICICR_S1_GINT_MODE __BIT(1)
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#define MMCR_PICICR_M_GINT_MODE __BIT(0)
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#define MMCR_MPICMODE 0xd02
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#define MMCR_SL1PICMODE 0xd03
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#define MMCR_SL2PICMODE 0xd04
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#define MMCR_WPVMAP 0xd44
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#define MMCR_WPVMAP_RSVD0 __BITS(7, 5)
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/* map write-protection violations to an Elan SC520 interrupt priority,
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* 1 through 22
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*/
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#define MMCR_WPVMAP_INT_MAP __BITS(4, 0)
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/* no bits set -> disable */
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#define MMCR_WPVMAP_INT_OFF 0
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/* all bits set -> NMI */
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#define MMCR_WPVMAP_INT_NMI MMCR_WPVMAP_INT_MAP
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#define MMCR_ADDDECCTL 0x80
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#define MMCR_ADDDECCTL_WPV_INT_ENB __BIT(7)
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#define MMCR_WPVSTA 0x82
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#define MMCR_WPVSTA_WPV_STA __BIT(15)
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#define MMCR_WPVSTA_WPV_RSVD0 __BITS(14, 10)
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#define MMCR_WPVSTA_WPV_MSTR __BITS(9, 8)
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#define MMCR_WPVSTA_WPV_MSTR_CPU __SHIFTIN(0, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_PCI __SHIFTIN(1, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_GP __SHIFTIN(2, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_MSTR_RSVD __SHIFTIN(3, MMCR_WPVSTA_WPV_MSTR)
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#define MMCR_WPVSTA_WPV_RSVD1 __BITS(7, 4)
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#define MMCR_WPVSTA_WPV_WINDOW __BITS(3, 0)
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#define MMCR_PAR(__i) (0x88 + 4 * (__i))
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#define MMCR_PAR_TARGET __BITS(31, 29)
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#define MMCR_PAR_TARGET_OFF __SHIFTIN(0, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_GPIO __SHIFTIN(1, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_GPMEM __SHIFTIN(2, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_PCI __SHIFTIN(3, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_BOOTCS __SHIFTIN(4, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_ROMCS1 __SHIFTIN(5, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_ROMCS2 __SHIFTIN(6, MMCR_PAR_TARGET)
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#define MMCR_PAR_TARGET_SDRAM __SHIFTIN(7, MMCR_PAR_TARGET)
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#define MMCR_PAR_ATTR __BITS(28, 26)
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#define MMCR_PAR_ATTR_NOEXEC __SHIFTIN(__BIT(2), MMCR_PAR_ATTR)
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#define MMCR_PAR_ATTR_NOCACHE __SHIFTIN(__BIT(1), MMCR_PAR_ATTR)
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#define MMCR_PAR_ATTR_NOWRITE __SHIFTIN(__BIT(0), MMCR_PAR_ATTR)
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#define MMCR_PAR_PG_SZ __BIT(25)
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#define MMCR_PAR_SZ_ST_ADR __BITS(24, 0)
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#define MMCR_PAR_4KB_SZ __BITS(24, 18)
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#define MMCR_PAR_4KB_ST_ADR __BITS(17, 0)
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#define MMCR_PAR_64KB_SZ __BITS(24, 14)
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#define MMCR_PAR_64KB_ST_ADR __BITS(13, 0)
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#define MMCR_PAR_IO_SZ __BITS(24, 16)
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#define MMCR_PAR_IO_ST_ADR __BITS(15, 0)
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/*
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* General Purpose Bus Registers
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*/
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#define MMCR_GPECHO 0x0c00 /* GP echo mode */
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#define MMCR_GPCSDW 0x0c01 /* GP chip sel data width */
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#define MMCR_CPCSQUAL 0x0c02 /* GP chip sel qualification */
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#define MMCR_GPCSRT 0x0c08 /* GP chip sel recovery time */
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#define MMCR_GPCSPW 0x0c09 /* GP chip sel pulse width */
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#define MMCR_GPCSOFF 0x0c0a /* GP chip sel offset */
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#define MMCR_GPRDW 0x0c0b /* GP read pulse width */
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#define MMCR_GPRDOFF 0x0c0c /* GP read offset */
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#define MMCR_GPWRW 0x0c0d /* GP write pulse width */
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#define MMCR_GPWROFF 0x0c0e /* GP write offset */
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#define MMCR_GPALEW 0x0c0f /* GPALE pulse width */
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#define MMCR_GPALEOFF 0x0c10 /* GPALE offset */
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#define GPECHO_GP_ECHO_ENB 0x01 /* GP bus echo mode enable */
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/*
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* Programmable Input/Output Registers
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*/
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#define MMCR_PIOPFS15_0 0x0c20 /* PIO15-PIO0 pin func sel */
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#define MMCR_PIOPFS31_16 0x0c22 /* PIO31-PIO16 pin func sel */
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#define MMCR_CSPFS 0x0c24 /* chip sel pin func sel */
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#define MMCR_CLKSEL 0x0c26 /* clock select */
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#define MMCR_DSCTL 0x0c28 /* drive strength control */
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#define MMCR_PIODIR15_0 0x0c2a /* PIO15-PIO0 direction */
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#define MMCR_PIODIR31_16 0x0c2c /* PIO31-PIO16 direction */
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#define MMCR_PIODATA15_0 0x0c30 /* PIO15-PIO0 data */
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#define MMCR_PIODATA31_16 0x0c32 /* PIO31-PIO16 data */
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#define MMCR_PIOSET15_0 0x0c34 /* PIO15-PIO0 set */
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#define MMCR_PIOSET31_16 0x0c36 /* PIO31-PIO16 set */
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#define MMCR_PIOCLR15_0 0x0c38 /* PIO15-PIO0 clear */
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#define MMCR_PIOCLR31_16 0x0c3a /* PIO31-PIO16 clear */
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#define ELANSC_PIO_NPINS 32 /* total number of PIO pins */
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/*
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* Watchdog Timer Registers.
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*/
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#define MMCR_WDTMRCTL 0x0cb0 /* watchdog timer control */
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#define MMCR_WDTMRCNTL 0x0cb2 /* watchdog timer count low */
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#define MMCR_WDTMRCNTH 0x0cb4 /* watchdog timer count high */
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#define WDTMRCTL_EXP_SEL_MASK 0x00ff /* exponent select */
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#define WDTMRCTL_EXP_SEL14 0x0001 /* 496us/492us */
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#define WDTMRCTL_EXP_SEL24 0x0002 /* 508ms/503ms */
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#define WDTMRCTL_EXP_SEL25 0x0004 /* 1.02s/1.01s */
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#define WDTMRCTL_EXP_SEL26 0x0008 /* 2.03s/2.01s */
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#define WDTMRCTL_EXP_SEL27 0x0010 /* 4.07s/4.03s */
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#define WDTMRCTL_EXP_SEL28 0x0020 /* 8.13s/8.05s */
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#define WDTMRCTL_EXP_SEL29 0x0040 /* 16.27s/16.11s */
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#define WDTMRCTL_EXP_SEL30 0x0080 /* 32.54s/32.21s */
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#define WDTMRCTL_IRQ_FLG 0x1000 /* interrupt request */
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#define WDTMRCTL_WRST_ENB 0x4000 /* watchdog timer reset enable */
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#define WDTMRCTL_ENB 0x8000 /* watchdog timer enable */
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#define WDTMRCTL_UNLOCK1 0x3333
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#define WDTMRCTL_UNLOCK2 0xcccc
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#define WDTMRCTL_RESET1 0xaaaa
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#define WDTMRCTL_RESET2 0x5555
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/*
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* Reset Generation Registers.
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*/
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#define MMCR_SYSINFO 0x0d70 /* system board information */
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#define MMCR_RESCFG 0x0d72 /* reset configuration */
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#define MMCR_RESSTA 0x0d74 /* reset status */
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#define RESCFG_SYS_RST 0x01 /* software system reset */
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#define RESCFG_GP_RST 0x02 /* assert GP bus reset */
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#define RESCFG_PRG_RST_ENB 0x04 /* programmable reset enable */
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#define RESCFG_ICE_ON_RST 0x08 /* enter AMDebug(tm) on reset */
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#define RESSTA_PWRGOOD_DET 0x01 /* POWERGOOD reset detect */
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#define RESSTA_PRGRST_DET 0x02 /* programmable reset detect */
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#define RESSTA_SD_RST_DET 0x04 /* CPU shutdown reset detect */
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#define RESSTA_WDT_RST_DET 0x08 /* watchdog timer reset detect */
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#define RESSTA_ICE_SRST_DET 0x10 /* AMDebug(tm) soft reset detect */
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#define RESSTA_ICE_HRST_DET 0x20 /* AMDebug(tm) soft reset detect */
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#define RESSTA_SCP_RST 0x40 /* SCP reset detect */
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#endif /* _I386_PCI_ELAN520REG_H_ */
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