383 lines
12 KiB
C
383 lines
12 KiB
C
/* $NetBSD: hcsc.c,v 1.12 2002/10/02 16:52:23 thorpej Exp $ */
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/*
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* Copyright (c) 2001 Ben Harris
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Mark Brinicombe of Causality Limited.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1996, 1997 Matthias Pfaller.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Matthias Pfaller.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* HCCS 8-bit SCSI driver using the generic NCR5380 driver
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*
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* Andy Armstrong gives some details of the HCCS SCSI cards at
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* <URL:http://www.armlinux.org/~webmail/linux-arm/1997-08/msg00042.html>.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: hcsc.c,v 1.12 2002/10/02 16:52:23 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/buf.h>
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#include <dev/scsipi/scsi_all.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsiconf.h>
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#include <dev/ic/ncr5380reg.h>
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#include <dev/ic/ncr5380var.h>
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#include <machine/bootconfig.h>
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#include <dev/podulebus/podulebus.h>
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#include <dev/podulebus/podules.h>
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#include <dev/podulebus/powerromreg.h>
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#include <dev/podulebus/hcscreg.h>
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void hcsc_attach (struct device *, struct device *, void *);
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int hcsc_match (struct device *, struct cfdata *, void *);
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static int hcsc_pdma_in(struct ncr5380_softc *, int, int, u_char *);
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static int hcsc_pdma_out(struct ncr5380_softc *, int, int, u_char *);
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/*
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* HCCS 8-bit SCSI softc structure.
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*
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* Contains the generic ncr5380 device node, podule information and
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* global information required by the driver.
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*/
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struct hcsc_softc {
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struct ncr5380_softc sc_ncr5380;
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bus_space_tag_t sc_pdmat;
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bus_space_handle_t sc_pdmah;
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void *sc_ih;
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struct evcnt sc_intrcnt;
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};
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CFATTACH_DECL(hcsc, sizeof(struct hcsc_softc),
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hcsc_match, hcsc_attach, NULL, NULL);
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/*
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* Card probe function
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*
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* Just match the manufacturer and podule ID's
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*/
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int
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hcsc_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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struct podulebus_attach_args *pa = aux;
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/* Normal ROM */
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if (pa->pa_product == PODULE_HCCS_IDESCSI &&
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strncmp(pa->pa_descr, "SCSI", 4) == 0)
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return 1;
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/* PowerROM */
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if (pa->pa_product == PODULE_ALSYSTEMS_SCSI &&
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podulebus_initloader(pa) == 0 &&
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podloader_callloader(pa, 0, 0) == PRID_HCCS_SCSI1)
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return 1;
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return 0;
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}
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/*
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* Card attach function
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*
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*/
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void
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hcsc_attach(struct device *parent, struct device *self, void *aux)
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{
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struct hcsc_softc *sc = (struct hcsc_softc *)self;
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struct podulebus_attach_args *pa = aux;
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#ifndef NCR5380_USE_BUS_SPACE
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u_char *iobase;
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#endif
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char hi_option[sizeof(sc->sc_ncr5380.sc_dev.dv_xname) + 8];
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sc->sc_ncr5380.sc_min_dma_len = 0;
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sc->sc_ncr5380.sc_no_disconnect = 0;
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sc->sc_ncr5380.sc_parity_disable = 0;
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sc->sc_ncr5380.sc_dma_alloc = NULL;
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sc->sc_ncr5380.sc_dma_free = NULL;
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sc->sc_ncr5380.sc_dma_poll = NULL;
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sc->sc_ncr5380.sc_dma_setup = NULL;
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sc->sc_ncr5380.sc_dma_start = NULL;
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sc->sc_ncr5380.sc_dma_eop = NULL;
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sc->sc_ncr5380.sc_dma_stop = NULL;
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sc->sc_ncr5380.sc_intr_on = NULL;
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sc->sc_ncr5380.sc_intr_off = NULL;
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#ifdef NCR5380_USE_BUS_SPACE
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sc->sc_ncr5380.sc_regt = pa->pa_fast_t;
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bus_space_map(sc->sc_ncr5380.sc_regt,
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pa->pa_fast_base + HCSC_DP8490_OFFSET, 8, 0,
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&sc->sc_ncr5380.sc_regh);
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sc->sc_ncr5380.sci_r0 = 0;
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sc->sc_ncr5380.sci_r1 = 1;
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sc->sc_ncr5380.sci_r2 = 2;
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sc->sc_ncr5380.sci_r3 = 3;
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sc->sc_ncr5380.sci_r4 = 4;
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sc->sc_ncr5380.sci_r5 = 5;
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sc->sc_ncr5380.sci_r6 = 6;
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sc->sc_ncr5380.sci_r7 = 7;
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#else
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iobase = (u_char *)pa->pa_fast_base + HCSC_DP8490_OFFSET;
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sc->sc_ncr5380.sci_r0 = iobase + 0;
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sc->sc_ncr5380.sci_r1 = iobase + 4;
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sc->sc_ncr5380.sci_r2 = iobase + 8;
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sc->sc_ncr5380.sci_r3 = iobase + 12;
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sc->sc_ncr5380.sci_r4 = iobase + 16;
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sc->sc_ncr5380.sci_r5 = iobase + 20;
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sc->sc_ncr5380.sci_r6 = iobase + 24;
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sc->sc_ncr5380.sci_r7 = iobase + 28;
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#endif
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sc->sc_pdmat = pa->pa_mod_t;
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bus_space_map(sc->sc_pdmat, pa->pa_mod_base + HCSC_PDMA_OFFSET, 1, 0,
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&sc->sc_pdmah);
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sc->sc_ncr5380.sc_rev = NCR_VARIANT_DP8490;
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sc->sc_ncr5380.sc_pio_in = hcsc_pdma_in;
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sc->sc_ncr5380.sc_pio_out = hcsc_pdma_out;
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/* Provide an override for the host id */
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sc->sc_ncr5380.sc_channel.chan_id = 7;
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sprintf(hi_option, "%s.hostid", sc->sc_ncr5380.sc_dev.dv_xname);
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(void)get_bootconf_option(boot_args, hi_option,
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BOOTOPT_TYPE_INT, &sc->sc_ncr5380.sc_channel.chan_id);
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sc->sc_ncr5380.sc_adapter.adapt_minphys = minphys;
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printf(": host ID %d\n", sc->sc_ncr5380.sc_channel.chan_id);
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evcnt_attach_dynamic(&sc->sc_intrcnt, EVCNT_TYPE_INTR, NULL,
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self->dv_xname, "intr");
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sc->sc_ih = podulebus_irq_establish(pa->pa_ih, IPL_BIO, ncr5380_intr,
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sc, &sc->sc_intrcnt);
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ncr5380_attach(&sc->sc_ncr5380);
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}
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#ifndef HCSC_TSIZE_OUT
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#define HCSC_TSIZE_OUT 512
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#endif
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#ifndef HCSC_TSIZE_IN
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#define HCSC_TSIZE_IN 512
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#endif
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#define TIMEOUT 1000000
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static __inline int
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hcsc_ready(struct ncr5380_softc *sc)
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{
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int i;
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for (i = TIMEOUT; i > 0; i--) {
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if ((NCR5380_READ(sc,sci_csr) &
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(SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH)) ==
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(SCI_CSR_DREQ | SCI_CSR_PHASE_MATCH))
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return(1);
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if ((NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
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SCI_BUSY(sc) == 0)
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return(0);
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}
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printf("%s: ready timeout\n", sc->sc_dev.dv_xname);
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return(0);
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}
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/* Return zero on success. */
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static __inline void hcsc_wait_not_req(struct ncr5380_softc *sc)
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{
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int timo;
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for (timo = TIMEOUT; timo; timo--) {
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if ((NCR5380_READ(sc, sci_bus_csr) & SCI_BUS_REQ) == 0 ||
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(NCR5380_READ(sc, sci_csr) & SCI_CSR_PHASE_MATCH) == 0 ||
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SCI_BUSY(sc) == 0) {
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return;
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}
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}
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printf("%s: pdma not_req timeout\n", sc->sc_dev.dv_xname);
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}
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static int
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hcsc_pdma_in(struct ncr5380_softc *ncr_sc, int phase, int datalen,
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u_char *data)
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{
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struct hcsc_softc *sc = (void *)ncr_sc;
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bus_space_tag_t pdmat = sc->sc_pdmat;
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bus_space_handle_t pdmah = sc->sc_pdmah;
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int s, resid, len;
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s = splbio();
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NCR5380_WRITE(ncr_sc, sci_mode,
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NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
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NCR5380_WRITE(ncr_sc, sci_irecv, 0);
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resid = datalen;
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while (resid > 0) {
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len = min(resid, HCSC_TSIZE_IN);
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if (hcsc_ready(ncr_sc) == 0)
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goto interrupt;
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bus_space_read_multi_1(pdmat, pdmah, 0, data, len);
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data += len;
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resid -= len;
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}
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hcsc_wait_not_req(ncr_sc);
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interrupt:
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SCI_CLR_INTR(ncr_sc);
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NCR5380_WRITE(ncr_sc, sci_mode,
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NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
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splx(s);
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return datalen - resid;
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}
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static int
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hcsc_pdma_out(struct ncr5380_softc *ncr_sc, int phase, int datalen,
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u_char *data)
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{
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struct hcsc_softc *sc = (void *)ncr_sc;
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bus_space_tag_t pdmat = sc->sc_pdmat;
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bus_space_handle_t pdmah = sc->sc_pdmah;
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int i, s, icmd, resid;
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s = splbio();
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icmd = NCR5380_READ(ncr_sc, sci_icmd) & SCI_ICMD_RMASK;
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NCR5380_WRITE(ncr_sc, sci_icmd, icmd | SCI_ICMD_DATA);
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NCR5380_WRITE(ncr_sc, sci_mode,
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NCR5380_READ(ncr_sc, sci_mode) | SCI_MODE_DMA);
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NCR5380_WRITE(ncr_sc, sci_dma_send, 0);
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resid = datalen;
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if (hcsc_ready(ncr_sc) == 0)
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goto interrupt;
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if (resid > HCSC_TSIZE_OUT) {
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/*
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* Because of the chips DMA prefetch, phase changes
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* etc, won't be detected until we have written at
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* least one byte more. We pre-write 4 bytes so
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* subsequent transfers will be aligned to a 4 byte
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* boundary. Assuming disconects will only occur on
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* block boundaries, we then correct for the pre-write
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* when and if we get a phase change. If the chip had
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* DMA byte counting hardware, the assumption would not
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* be necessary.
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*/
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bus_space_write_multi_1(pdmat, pdmah, 0, data, 4);
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data += 4;
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resid -= 4;
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for (; resid >= HCSC_TSIZE_OUT; resid -= HCSC_TSIZE_OUT) {
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if (hcsc_ready(ncr_sc) == 0) {
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resid += 4; /* Overshot */
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goto interrupt;
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}
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bus_space_write_multi_1(pdmat, pdmah, 0, data,
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HCSC_TSIZE_OUT);
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data += HCSC_TSIZE_OUT;
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}
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if (hcsc_ready(ncr_sc) == 0) {
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resid += 4; /* Overshot */
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goto interrupt;
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}
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}
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if (resid) {
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bus_space_write_multi_1(pdmat, pdmah, 0, data, resid);
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resid = 0;
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}
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for (i = TIMEOUT; i > 0; i--) {
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if ((NCR5380_READ(ncr_sc, sci_csr)
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& (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH))
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!= SCI_CSR_DREQ)
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break;
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}
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if (i != 0)
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bus_space_write_1(pdmat, pdmah, 0, 0);
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else
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printf("%s: timeout waiting for final SCI_DSR_DREQ.\n",
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ncr_sc->sc_dev.dv_xname);
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hcsc_wait_not_req(ncr_sc);
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interrupt:
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SCI_CLR_INTR(ncr_sc);
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NCR5380_WRITE(ncr_sc, sci_mode,
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NCR5380_READ(ncr_sc, sci_mode) & ~SCI_MODE_DMA);
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NCR5380_WRITE(ncr_sc, sci_icmd, icmd);
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splx(s);
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return(datalen - resid);
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}
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