623 lines
18 KiB
C
623 lines
18 KiB
C
/* $OpenBSD: generic2e_machdep.c,v 1.2 2011/04/15 20:40:06 deraadt Exp $ */
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/*
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* Copyright (c) 2010 Miodrag Vallat.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*-
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* Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Generic Loongson 2E code and configuration data.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: generic2e_machdep.c,v 1.5 2015/06/09 16:10:48 macallan Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/device.h>
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#include <sys/types.h>
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#include <dev/ic/i8259reg.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcidevs.h>
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#include <mips/cpuregs.h>
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#include <mips/bonito/bonitoreg.h>
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#include <mips/bonito/bonitovar.h>
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#include <evbmips/loongson/autoconf.h>
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#include <mips/pmon/pmon.h>
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#include <evbmips/loongson/loongson_intr.h>
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#include <evbmips/loongson/loongson_isa.h>
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#include <evbmips/loongson/loongson_bus_defs.h>
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#include "com.h"
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#include "isa.h"
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#if NCOM > 0
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#include <sys/termios.h>
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#include <dev/ic/comvar.h>
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#endif
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void generic2e_device_register(device_t, void *);
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void generic2e_reset(void);
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void generic2e_setup(void);
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void generic2e_pci_attach_hook(device_t, device_t,
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struct pcibus_attach_args *);
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int generic2e_intr_map(int, int, int, pci_intr_handle_t *);
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void generic2e_isa_attach_hook(device_t, device_t,
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struct isabus_attach_args *);
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void *generic2e_isa_intr_establish(void *, int, int, int,
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int (*)(void *), void *);
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void generic2e_isa_intr_disestablish(void *, void *);
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const struct evcnt * generic2e_isa_intr_evcnt(void *, int);
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const char * generic2e_isa_intr_string(void *, int, char *, size_t);
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void generic2e_isa_intr(int, vaddr_t, uint32_t);
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void via686sb_setup(pci_chipset_tag_t, int);
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/* PnP IRQ assignment for VIA686 SuperIO components */
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#define VIA686_IRQ_PCIA 9
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#define VIA686_IRQ_PCIB 10
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#define VIA686_IRQ_PCIC 11
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#define VIA686_IRQ_PCID 13
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static int generic2e_via686sb_dev = -1;
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const struct bonito_config generic2e_bonito = {
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.bc_adbase = 11,
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.bc_gpioIE = 0xffffffff,
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.bc_intEdge = BONITO_INTRMASK_SYSTEMERR | BONITO_INTRMASK_MASTERERR |
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BONITO_INTRMASK_RETRYERR | BONITO_INTRMASK_MBOX,
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.bc_intSteer = 0,
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.bc_intPol = 0,
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.bc_attach_hook = generic2e_pci_attach_hook,
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};
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const struct legacy_io_range generic2e_legacy_ranges[] = {
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/* no isa space access restrictions */
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{ 0, BONITO_PCIIO_LEGACY },
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{ 0 }
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};
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struct mips_isa_chipset generic2e_isa_chipset = {
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.ic_v = NULL,
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.ic_attach_hook = generic2e_isa_attach_hook,
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.ic_intr_establish = generic2e_isa_intr_establish,
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.ic_intr_disestablish = generic2e_isa_intr_disestablish,
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.ic_intr_evcnt = generic2e_isa_intr_evcnt,
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.ic_intr_string = generic2e_isa_intr_string,
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};
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const struct platform generic2e_platform = {
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.system_type = LOONGSON_2E,
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.vendor = "Generic",
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.product = "Loongson2E",
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.bonito_config = &generic2e_bonito,
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.isa_chipset = &generic2e_isa_chipset,
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.legacy_io_ranges = generic2e_legacy_ranges,
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.bonito_mips_intr = MIPS_INT_MASK_0,
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.isa_mips_intr = MIPS_INT_MASK_3,
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.isa_intr = generic2e_isa_intr,
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.p_pci_intr_map = generic2e_intr_map,
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.irq_map = loongson2e_irqmap,
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.setup = generic2e_setup,
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.device_register = generic2e_device_register,
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.powerdown = NULL,
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.reset = generic2e_reset
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};
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/*
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* PCI model specific routines
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*/
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void
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generic2e_pci_attach_hook(device_t parent, device_t self,
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struct pcibus_attach_args *pba)
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{
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pci_chipset_tag_t pc = pba->pba_pc;
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pcireg_t id;
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pcitag_t tag;
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int dev;
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if (pba->pba_bus != 0)
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return;
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/*
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* Check for a VIA 686 southbridge; if one is found, remember
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* its location, needed by generic2e_intr_map().
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*/
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for (dev = pci_bus_maxdevs(pc, 0); dev >= 0; dev--) {
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tag = pci_make_tag(pc, 0, dev, 0);
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id = pci_conf_read(pc, tag, PCI_ID_REG);
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if (id == PCI_ID_CODE(PCI_VENDOR_VIATECH,
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PCI_PRODUCT_VIATECH_VT82C686A_ISA)) {
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generic2e_via686sb_dev = dev;
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break;
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}
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}
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if (generic2e_via686sb_dev != 0)
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via686sb_setup(pc, generic2e_via686sb_dev);
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}
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int
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generic2e_intr_map(int dev, int fn, int pin, pci_intr_handle_t *ihp)
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{
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if (dev == generic2e_via686sb_dev) {
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switch (fn) {
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case 1: /* PCIIDE */
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/* will use compat interrupt */
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break;
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case 2: /* USB */
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*ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIB);
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return 0;
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case 3: /* USB */
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*ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIC);
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return 0;
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case 4: /* power management, SMBus */
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break;
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case 5: /* Audio */
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*ihp = BONITO_ISA_IRQ(VIA686_IRQ_PCIA);
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return 0;
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case 6: /* Modem */
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break;
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default:
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break;
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}
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} else {
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*ihp = BONITO_DIRECT_IRQ(BONITO_INTR_GPIN +
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pin - PCI_INTERRUPT_PIN_A);
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return 0;
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}
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return 1;
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}
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/*
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* ISA model specific routines
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*/
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void
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generic2e_isa_attach_hook(device_t parent, device_t self,
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struct isabus_attach_args *iba)
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{
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loongson_set_isa_imr(loongson_isaimr);
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}
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void *
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generic2e_isa_intr_establish(void *v, int irq, int type, int level,
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int (*handler)(void *), void *arg)
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{
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void *ih;
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uint imr;
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ih = evbmips_intr_establish(BONITO_ISA_IRQ(irq), handler, arg);
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if (ih == NULL)
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return NULL;
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/* enable interrupt */
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imr = loongson_isaimr;
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imr |= (1 << irq);
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loongson_set_isa_imr(imr);
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return ih;
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}
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void
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generic2e_isa_intr_disestablish(void *v, void *ih)
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{
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evbmips_intr_disestablish(ih);
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}
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const struct evcnt *
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generic2e_isa_intr_evcnt(void *v, int irq)
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{
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if (irq == 0 || irq >= BONITO_NISA || irq == 2)
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panic("generic2e_isa_intr_evcnt: bogus isa irq 0x%x", irq);
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return (&bonito_intrhead[BONITO_ISA_IRQ(irq)].intr_count);
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}
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const char *
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generic2e_isa_intr_string(void *v, int irq, char *buf, size_t len)
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{
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if (irq == 0 || irq >= BONITO_NISA || irq == 2)
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panic("generic2e_isa_intr_string: bogus isa irq 0x%x", irq);
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return loongson_intr_string(&generic2e_bonito, irq, buf, len);
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}
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void
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generic2e_isa_intr(int ipl, vaddr_t pc, uint32_t ipending)
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{
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#if NISA > 0
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struct evbmips_intrhand *ih;
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uint64_t isr, mask = 0;
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int rc, irq, ret;
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uint8_t ocw1, ocw2;
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for (;;) {
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =
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OCW3_SELECT | OCW3_POLL;
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ocw1 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3);
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if ((ocw1 & OCW3_POLL_PENDING) == 0)
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break;
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irq = OCW3_POLL_IRQ(ocw1);
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if (irq == 2) /* cascade */ {
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =
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OCW3_SELECT | OCW3_POLL;
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ocw2 = REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3);
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if (ocw2 & OCW3_POLL_PENDING)
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irq = OCW3_POLL_IRQ(ocw2);
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else
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irq = 2;
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} else
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ocw2 = 0;
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/*
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* Mask the interrupt before servicing it.
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*/
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isr = 1UL << irq;
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loongson_set_isa_imr(loongson_isaimr & ~isr);
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mask |= isr;
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rc = 0;
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LIST_FOREACH(ih,
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&bonito_intrhead[BONITO_ISA_IRQ(irq)].intrhand_head,
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ih_q) {
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ret = (*ih->ih_func)(ih->ih_arg);
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if (ret) {
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rc = 1;
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bonito_intrhead[BONITO_ISA_IRQ(irq)].intr_count.ev_count++;
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}
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if (ret == 1)
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break;
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}
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/* Send a specific EOI to the 8259. */
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loongson_isa_specific_eoi(irq);
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if (rc == 0) {
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printf("spurious isa interrupt %d\n", irq);
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}
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}
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/*
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* Reenable interrupts which have been serviced.
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*/
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if (mask != 0)
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loongson_set_isa_imr(loongson_isaimr | mask);
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#endif
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}
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/*
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* Other model specific routines
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*/
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void
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generic2e_reset(void)
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{
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REGVAL(BONITO_BONGENCFG) &= ~BONITO_BONGENCFG_CPUSELFRESET;
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REGVAL(BONITO_BONGENCFG) |= BONITO_BONGENCFG_CPUSELFRESET;
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delay(1000000);
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}
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void
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generic2e_setup(void)
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{
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#if NCOM > 0
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const char *envvar;
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int serial;
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envvar = pmon_getenv("nokbd");
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serial = envvar != NULL;
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envvar = pmon_getenv("novga");
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serial = serial && envvar != NULL;
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if (serial) {
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comconsiot = &bonito_iot;
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comconsaddr = 0x3f8;
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comconsrate = 115200; /* default PMON console speed */
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}
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#endif
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}
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void
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generic2e_device_register(device_t dev, void *aux)
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{
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const char *name = device_xname(dev);
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if (device_class(dev) != bootdev_class)
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return;
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/*
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* The device numbering must match. There's no way
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* pmon tells us more info. Depending on the usb slot
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* and hubs used you may be lucky. Also, assume umass/sd for usb
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* attached devices.
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*/
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switch (bootdev_class) {
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case DV_DISK:
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if (device_is_a(dev, "wd") && strcmp(name, bootdev) == 0) {
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if (booted_device == NULL)
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booted_device = dev;
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} else {
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/* XXX this really only works safely for usb0... */
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if ((device_is_a(dev, "sd") ||
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device_is_a(dev, "cd")) &&
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strncmp(bootdev, "usb", 3) == 0 &&
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strcmp(name + 2, bootdev + 3) == 0) {
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if (booted_device == NULL)
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booted_device = dev;
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}
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}
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break;
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case DV_IFNET:
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/*
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* This relies on the onboard Ethernet interface being
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* attached before any other (usb) interface.
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*/
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if (booted_device == NULL)
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booted_device = dev;
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break;
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default:
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break;
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}
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}
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/*
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* Initialize a VIA686 south bridge.
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*
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* PMON apparently does not perform enough initialization; one may argue this
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* could be done with a specific pcib(4) driver, but then no other system
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* will hopefully need this, so keep it local to the 2E setup code.
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*/
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#define VIA686_ISA_ROM_CONTROL 0x40
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#define VIA686_ROM_WRITE_ENABLE 0x00000001
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#define VIA686_NO_ROM_WAIT_STATE 0x00000002
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#define VIA686_EXTEND_ALE 0x00000004
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#define VIA686_IO_RECOVERY_TIME 0x00000008
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#define VIA686_CHIPSET_EXTRA_WAIT_STATES 0x00000010
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#define VIA686_ISA_EXTRA_WAIT_STATES 0x00000020
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#define VIA686_ISA_EXTENDED_BUS_READY 0x00000040
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#define VIA686_ISA_EXTRA_COMMAND_DELAY 0x00000080
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#define VIA686_ISA_REFRESH 0x00000100
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#define VIA686_DOUBLE_DMA_CLOCK 0x00000800
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#define VIA686_PORT_92_FAST_RESET 0x00002000
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#define VIA686_IO_MEDIUM_RECOVERY_TIME 0x00004000
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#define VIA686_KBC_DMA_MISC12 0x44
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#define VIA686_ISA_MASTER_TO_LINE_BUFFER 0x00008000
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#define VIA686_POSTED_MEMORY_WRITE_ENABLE 0x00010000
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#define VIA686_PCI_BURST_INTERRUPTABLE 0x00020000
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#define VIA686_FLUSH_LINE_BUFFER_ON_INTR 0x00200000
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#define VIA686_GATE_INTR 0x00400000
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#define VIA686_PCI_MASTER_WRITE_WAIT_STATE 0x00800000
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#define VIA686_PCI_RESET 0x01000000
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#define VIA686_PCI_READ_DELAY_TRANSACTION_TMO 0x02000000
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#define VIA686_PCI_WRITE_DELAY_TRANSACTION_TMO 0x04000000
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#define VIA686_ICR_SHADOW_ENABLE 0x10000000
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#define VIA686_EISA_PORT_4D0_4D1_ENABLE 0x20000000
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#define VIA686_PCI_DELAY_TRANSACTION_ENABLE 0x40000000
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#define VIA686_CPU_RESET_SOURCE_INIT 0x80000000
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#define VIA686_MISC3_IDE_INTR 0x48
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#define VIA686_IDE_PRIMARY_CHAN_MASK 0x00030000
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#define VIA686_IDE_PRIMARY_CHAN_SHIFT 16
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#define VIA686_IDE_SECONDARY_CHAN_MASK 0x000c0000
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#define VIA686_IDE_SECONDARY_CHAN_SHIFT 18
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#define VIA686_IDE_IRQ14 00
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#define VIA686_IDE_IRQ15 01
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#define VIA686_IDE_IRQ10 02
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#define VIA686_IDE_IRQ11 03
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#define VIA686_IDE_PGNT 0x00800000
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#define VIA686_PNP_DMA_IRQ 0x50
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#define VIA686_DMA_FDC_MASK 0x00000003
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#define VIA686_DMA_FDC_SHIFT 0
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#define VIA686_DMA_LPT_MASK 0x0000000c
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#define VIA686_DMA_LPT_SHIFT 2
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#define VIA686_IRQ_FDC_MASK 0x00000f00
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#define VIA686_IRQ_FDC_SHIFT 8
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#define VIA686_IRQ_LPT_MASK 0x0000f000
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#define VIA686_IRQ_LPT_SHIFT 12
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#define VIA686_IRQ_COM0_MASK 0x000f0000
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#define VIA686_IRQ_COM0_SHIFT 16
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#define VIA686_IRQ_COM1_MASK 0x00f00000
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#define VIA686_IRQ_COM1_SHIFT 20
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#define VIA686_PCI_LEVEL_PNP_IRQ2 0x54
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#define VIA686_PCI_IRQD_EDGE 0x00000001
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#define VIA686_PCI_IRQC_EDGE 0x00000002
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#define VIA686_PCI_IRQB_EDGE 0x00000004
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#define VIA686_PCI_IRQA_EDGE 0x00000008
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#define VIA686_IRQ_PCIA_MASK 0x0000f000
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#define VIA686_IRQ_PCIA_SHIFT 12
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#define VIA686_IRQ_PCIB_MASK 0x000f0000
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#define VIA686_IRQ_PCIB_SHIFT 16
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#define VIA686_IRQ_PCIC_MASK 0x00f00000
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#define VIA686_IRQ_PCIC_SHIFT 20
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#define VIA686_IRQ_PCID_MASK 0xf0000000
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#define VIA686_IRQ_PCID_SHIFT 28
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void
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via686sb_setup(pci_chipset_tag_t pc, int dev)
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{
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pcitag_t tag;
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pcireg_t reg;
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uint elcr;
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tag = pci_make_tag(pc, 0, dev, 0);
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/*
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* Generic ISA bus initialization.
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*/
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reg = pci_conf_read(pc, tag, VIA686_ISA_ROM_CONTROL);
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reg |= VIA686_IO_RECOVERY_TIME | VIA686_ISA_REFRESH;
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pci_conf_write(pc, tag, VIA686_ISA_ROM_CONTROL, reg);
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reg = pci_conf_read(pc, tag, VIA686_KBC_DMA_MISC12);
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reg |= VIA686_CPU_RESET_SOURCE_INIT |
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VIA686_PCI_DELAY_TRANSACTION_ENABLE |
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VIA686_EISA_PORT_4D0_4D1_ENABLE |
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VIA686_PCI_WRITE_DELAY_TRANSACTION_TMO |
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VIA686_PCI_READ_DELAY_TRANSACTION_TMO |
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VIA686_PCI_MASTER_WRITE_WAIT_STATE | VIA686_GATE_INTR |
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VIA686_FLUSH_LINE_BUFFER_ON_INTR;
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reg &= ~VIA686_ISA_MASTER_TO_LINE_BUFFER;
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pci_conf_write(pc, tag, VIA686_KBC_DMA_MISC12, reg);
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/*
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* SuperIO devices interrupt and DMA setup.
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*/
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reg = pci_conf_read(pc, tag, VIA686_MISC3_IDE_INTR);
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reg &= ~(VIA686_IDE_PRIMARY_CHAN_MASK | VIA686_IDE_SECONDARY_CHAN_MASK);
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reg |= (VIA686_IDE_IRQ14 << VIA686_IDE_PRIMARY_CHAN_SHIFT);
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reg |= (VIA686_IDE_IRQ15 << VIA686_IDE_SECONDARY_CHAN_SHIFT);
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reg |= VIA686_IDE_PGNT;
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pci_conf_write(pc, tag, VIA686_MISC3_IDE_INTR, reg);
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reg = pci_conf_read(pc, tag, VIA686_PNP_DMA_IRQ);
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reg &= ~(VIA686_DMA_FDC_MASK | VIA686_DMA_LPT_MASK);
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reg |= (2 << VIA686_DMA_FDC_SHIFT) | (3 << VIA686_DMA_LPT_SHIFT);
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reg &= ~(VIA686_IRQ_FDC_MASK | VIA686_IRQ_LPT_MASK);
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reg |= (6 << VIA686_IRQ_FDC_SHIFT) | (7 << VIA686_IRQ_LPT_SHIFT);
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reg &= ~(VIA686_IRQ_COM0_MASK | VIA686_IRQ_COM1_MASK);
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reg |= (4 << VIA686_IRQ_COM0_SHIFT) | (3 << VIA686_IRQ_COM1_SHIFT);
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reg = pci_conf_read(pc, tag, VIA686_PCI_LEVEL_PNP_IRQ2);
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reg &= ~(VIA686_PCI_IRQA_EDGE | VIA686_PCI_IRQB_EDGE |
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VIA686_PCI_IRQB_EDGE | VIA686_PCI_IRQD_EDGE);
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reg &= ~(VIA686_IRQ_PCIA_MASK | VIA686_IRQ_PCIB_MASK |
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VIA686_IRQ_PCIC_MASK | VIA686_IRQ_PCID_MASK);
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reg |= (VIA686_IRQ_PCIA << VIA686_IRQ_PCIA_SHIFT) |
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(VIA686_IRQ_PCIB << VIA686_IRQ_PCIB_SHIFT) |
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(VIA686_IRQ_PCIC << VIA686_IRQ_PCIC_SHIFT) |
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(VIA686_IRQ_PCID << VIA686_IRQ_PCID_SHIFT);
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/*
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* Interrupt controller setup.
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*/
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/* reset; program device, four bytes */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW1) =
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ICW1_SELECT | ICW1_IC4;
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW2) = ICW2_VECTOR(0);
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW3) = ICW3_CASCADE(2);
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_ICW4) = ICW4_8086;
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/* leave interrupts masked */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW1) = 0xff;
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/* special mask mode (if available) */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) =
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OCW3_SELECT | OCW3_SSMM | OCW3_SMM;
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/* read IRR by default. */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU1 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
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/* reset; program device, four bytes */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW1) =
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ICW1_SELECT | ICW1_IC4;
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW2) = ICW2_VECTOR(8);
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW3) = ICW3_SIC(2);
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_ICW4) = ICW4_8086;
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/* leave interrupts masked */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW1) = 0xff;
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/* special mask mode (if available) */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) =
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OCW3_SELECT | OCW3_SSMM | OCW3_SMM;
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/* read IRR by default. */
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REGVAL8(BONITO_PCIIO_BASE + IO_ICU2 + PIC_OCW3) = OCW3_SELECT | OCW3_RR;
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/* setup ELCR: PCI interrupts are level-triggered. */
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elcr = (1 << VIA686_IRQ_PCIA) | (1 << VIA686_IRQ_PCIB) |
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(1 << VIA686_IRQ_PCIC) | (1 << VIA686_IRQ_PCID);
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REGVAL8(BONITO_PCIIO_BASE + 0x4d0) = (elcr >> 0) & 0xff;
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REGVAL8(BONITO_PCIIO_BASE + 0x4d1) = (elcr >> 8) & 0xff;
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__asm__ __volatile__ ("sync" ::: "memory");
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/*
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* Update interrupt information for secondary functions.
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* Although this information is not used by pci_intr_establish()
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* because of generic2e_intr_map() behaviour, it seems to be
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* required to complete proper interrupt routing.
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*/
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tag = pci_make_tag(pc, 0, dev, 2);
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reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
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reg |= VIA686_IRQ_PCIB << PCI_INTERRUPT_LINE_SHIFT;
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pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
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tag = pci_make_tag(pc, 0, dev, 3);
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reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
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reg |= VIA686_IRQ_PCIC << PCI_INTERRUPT_LINE_SHIFT;
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pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
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tag = pci_make_tag(pc, 0, dev, 5);
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reg = pci_conf_read(pc, tag, PCI_INTERRUPT_REG);
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reg &= ~(PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
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reg |= VIA686_IRQ_PCIA << PCI_INTERRUPT_LINE_SHIFT;
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pci_conf_write(pc, tag, PCI_INTERRUPT_REG, reg);
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}
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