515 lines
14 KiB
C
515 lines
14 KiB
C
/* $NetBSD: et4000.c,v 1.26 2014/07/25 08:10:32 dholland Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Julian Coleman.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Thanks to:
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* Leo Weppelman
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* 'Maximum Entropy'
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* Thomas Gerner
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* Juergen Orscheidt
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* for their help and for code that I could refer to when writing this driver.
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*
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* Defining DEBUG_ET4000 will cause the driver to *always* attach. Use for
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* debugging register settings.
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*/
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/*
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#define DEBUG_ET4000
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: et4000.c,v 1.26 2014/07/25 08:10:32 dholland Exp $");
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#include <sys/param.h>
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#include <sys/ioctl.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/event.h>
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#include <atari/vme/vmevar.h>
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#include <machine/iomap.h>
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#include <machine/video.h>
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#include <machine/mfp.h>
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#include <machine/cpu.h>
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#include <atari/atari/device.h>
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#include <atari/dev/grfioctl.h>
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#include <atari/dev/grf_etreg.h>
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#include "ioconf.h"
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/*
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* Allow a 8Kb io-region and a 1MB frame buffer to be mapped. This
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* is more or less required by the XFree server. The X server also
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* requires that the frame buffer be mapped above 0x3fffff.
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*/
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#define REG_MAPPABLE (8 * 1024) /* 0x2000 */
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#define FRAME_MAPPABLE (1 * 1024 * 1024) /* 0x100000 */
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#define FRAME_BASE (4 * 1024 * 1024) /* 0x400000 */
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#define VGA_MAPPABLE (128 * 1024) /* 0x20000 */
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#define VGA_BASE 0xa0000
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static int et4k_vme_match(device_t, cfdata_t, void *);
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static void et4k_vme_attach(device_t, device_t, void *);
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static int et4k_probe_addresses(struct vme_attach_args *);
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static void et4k_start(bus_space_tag_t *, bus_space_handle_t *, int *,
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u_char *);
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static void et4k_stop(bus_space_tag_t *, bus_space_handle_t *, int *,
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u_char *);
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static int et4k_detect(bus_space_tag_t *, bus_space_tag_t *,
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bus_space_handle_t *, bus_space_handle_t *, u_int);
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int et4kon(dev_t);
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int et4koff(dev_t);
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/* Register and screen memory addresses for ET4000 based VME cards */
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static struct et4k_addresses {
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u_long io_addr;
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u_long io_size;
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u_long mem_addr;
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u_long mem_size;
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} et4kstd[] = {
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{ 0xfebf0000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Crazy Dots VME & II */
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{ 0xfed00000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE }, /* Spektrum I & HC */
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{ 0xfed80000, REG_MAPPABLE, 0xfec00000, FRAME_MAPPABLE } /* Spektrum TC */
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};
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#define NET4KSTD (sizeof(et4kstd) / sizeof(et4kstd[0]))
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struct grfabs_et4k_priv {
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volatile void * regkva;
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volatile void * memkva;
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int regsz;
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int memsz;
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} et4k_priv;
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struct et4k_softc {
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device_t sc_dev;
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bus_space_tag_t sc_iot;
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bus_space_tag_t sc_memt;
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bus_space_handle_t sc_ioh;
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bus_space_handle_t sc_memh;
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int sc_flags;
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int sc_iobase;
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int sc_maddr;
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int sc_iosize;
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int sc_msize;
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};
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#define ET_SC_FLAGS_INUSE 1
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CFATTACH_DECL_NEW(et4k, sizeof(struct et4k_softc),
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et4k_vme_match, et4k_vme_attach, NULL, NULL);
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dev_type_open(et4kopen);
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dev_type_close(et4kclose);
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dev_type_read(et4kread);
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dev_type_write(et4kwrite);
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dev_type_ioctl(et4kioctl);
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dev_type_mmap(et4kmmap);
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const struct cdevsw et4k_cdevsw = {
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.d_open = et4kopen,
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.d_close = et4kclose,
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.d_read = et4kread,
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.d_write = et4kwrite,
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.d_ioctl = et4kioctl,
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.d_stop = nostop,
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.d_tty = notty,
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.d_poll = nopoll,
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.d_mmap = et4kmmap,
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.d_kqfilter = nokqfilter,
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.d_discard = nodiscard,
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.d_flag = 0
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};
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/*
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* Look for a ET4000 (Crazy Dots) card on the VME bus. We might
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* match Spektrum cards too (untested).
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*/
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int
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et4k_vme_match(device_t parent, cfdata_t cf, void *aux)
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{
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struct vme_attach_args *va = aux;
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return et4k_probe_addresses(va);
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}
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static int
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et4k_probe_addresses(struct vme_attach_args *va)
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{
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int i, found = 0;
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bus_space_tag_t iot;
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bus_space_tag_t memt;
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bus_space_handle_t ioh;
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bus_space_handle_t memh;
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iot = va->va_iot;
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memt = va->va_memt;
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/* Loop around our possible addresses looking for a match */
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for (i = 0; i < NET4KSTD; i++) {
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struct et4k_addresses *et4k_ap = &et4kstd[i];
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struct vme_attach_args vat = *va;
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if (vat.va_irq != VMECF_IRQ_DEFAULT) {
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printf("%s: config error: no irq support\n", __func__);
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return 0;
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}
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if (vat.va_iobase == VMECF_IOPORT_DEFAULT)
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vat.va_iobase = et4k_ap->io_addr;
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if (vat.va_maddr == VMECF_MEM_DEFAULT)
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vat.va_maddr = et4k_ap->mem_addr;
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if (vat.va_iosize == VMECF_IOSIZE_DEFAULT)
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vat.va_iosize = et4k_ap->io_size;
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if (vat.va_msize == VMECF_MEMSIZ_DEFAULT)
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vat.va_msize = et4k_ap->mem_size;
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if (bus_space_map(iot, vat.va_iobase, vat.va_iosize, 0,
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&ioh)) {
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printf("%s: cannot map io area\n", __func__);
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return 0;
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}
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if (bus_space_map(memt, vat.va_maddr, vat.va_msize,
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BUS_SPACE_MAP_LINEAR|BUS_SPACE_MAP_CACHEABLE,
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&memh)) {
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bus_space_unmap(iot, ioh, vat.va_iosize);
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printf("%s: cannot map memory area\n", __func__);
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return 0;
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}
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found = et4k_detect(&iot, &memt, &ioh, &memh, vat.va_msize);
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bus_space_unmap(iot, ioh, vat.va_iosize);
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bus_space_unmap(memt, memh, vat.va_msize);
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if (found) {
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*va = vat;
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return 1;
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}
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}
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return 0;
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}
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static void
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et4k_start(bus_space_tag_t *iot, bus_space_handle_t *ioh, int *vgabase, u_char *saved)
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{
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/* Enable VGA */
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bus_space_write_1(*iot, *ioh, GREG_VIDEOSYSENABLE, 0x01);
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/* Check whether colour (base = 3d0) or mono (base = 3b0) mode */
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*vgabase = (bus_space_read_1(*iot, *ioh, GREG_MISC_OUTPUT_R) & 0x01)
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? 0x3d0 : 0x3b0;
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/* Enable 'Tseng Extensions' - writes to CRTC and ATC[16] */
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bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x03);
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bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0xa0);
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/* Set up 16 bit I/O, memory, Tseng addressing and linear mapping */
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bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x36);
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bus_space_write_1(*iot, *ioh, *vgabase + 0x05, 0xf0);
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/* Enable writes to CRTC[0..7] */
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bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11);
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*saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05);
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bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved & 0x7f);
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/* Map all memory for video modes */
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bus_space_write_1(*iot, *ioh, 0x3ce, 0x06);
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bus_space_write_1(*iot, *ioh, 0x3cf, 0x01);
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}
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static void
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et4k_stop(bus_space_tag_t *iot, bus_space_handle_t *ioh, int *vgabase, u_char *saved)
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{
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/* Restore writes to CRTC[0..7] */
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bus_space_write_1(*iot, *ioh, *vgabase + 0x04, 0x11);
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*saved = bus_space_read_1(*iot, *ioh, *vgabase + 0x05);
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bus_space_write_1(*iot, *ioh, *vgabase + 0x05, *saved | 0x80);
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/* Disable 'Tseng Extensions' */
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bus_space_write_1(*iot, *ioh, *vgabase + 0x08, 0x00);
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bus_space_write_1(*iot, *ioh, GREG_DISPMODECONTROL, 0x29);
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bus_space_write_1(*iot, *ioh, GREG_HERCULESCOMPAT, 0x01);
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}
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static int
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et4k_detect(bus_space_tag_t *iot, bus_space_tag_t *memt, bus_space_handle_t *ioh, bus_space_handle_t *memh, u_int memsize)
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{
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u_char orig, new, saved;
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int vgabase;
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/* Test accessibility of registers and memory */
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if (!bus_space_peek_1(*iot, *ioh, GREG_STATUS1_R))
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return 0;
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if (!bus_space_peek_1(*memt, *memh, 0))
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return 0;
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et4k_start(iot, ioh, &vgabase, &saved);
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/* Is the card a Tseng card? Check read/write of ATC[16] */
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(void)bus_space_read_1(*iot, *ioh, vgabase + 0x0a);
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bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20);
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orig = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R);
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bus_space_write_1(*iot, *ioh, ACT_ADDRESS_W, (orig ^ 0x10));
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bus_space_write_1(*iot, *ioh, ACT_ADDRESS, 0x16 | 0x20);
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new = bus_space_read_1(*iot, *ioh, ACT_ADDRESS_R);
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bus_space_write_1(*iot, *ioh, ACT_ADDRESS, orig);
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if (new != (orig ^ 0x10)) {
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#ifdef DEBUG_ET4000
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printf("et4000: ATC[16] failed (%x != %x)\n",
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new, (orig ^ 0x10));
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#else
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et4k_stop(iot, ioh, &vgabase, &saved);
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return 0;
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#endif
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}
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/* Is the card and ET4000? Check read/write of CRTC[33] */
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bus_space_write_1(*iot, *ioh, vgabase + 0x04, 0x33);
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orig = bus_space_read_1(*iot, *ioh, vgabase + 0x05);
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bus_space_write_1(*iot, *ioh, vgabase + 0x05, (orig ^ 0x0f));
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new = bus_space_read_1(*iot, *ioh, vgabase + 0x05);
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bus_space_write_1(*iot, *ioh, vgabase + 0x05, orig);
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if (new != (orig ^ 0x0f)) {
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#ifdef DEBUG_ET4000
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printf("et4000: CRTC[33] failed (%x != %x)\n",
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new, (orig ^ 0x0f));
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#else
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et4k_stop(iot, ioh, &vgabase, &saved);
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return 0;
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#endif
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}
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/* Set up video memory so we can read & write it */
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bus_space_write_1(*iot, *ioh, 0x3c4, 0x04);
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bus_space_write_1(*iot, *ioh, 0x3c5, 0x06);
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bus_space_write_1(*iot, *ioh, 0x3c4, 0x07);
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bus_space_write_1(*iot, *ioh, 0x3c5, 0xa8);
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bus_space_write_1(*iot, *ioh, 0x3ce, 0x01);
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bus_space_write_1(*iot, *ioh, 0x3cf, 0x00);
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bus_space_write_1(*iot, *ioh, 0x3ce, 0x03);
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bus_space_write_1(*iot, *ioh, 0x3cf, 0x00);
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bus_space_write_1(*iot, *ioh, 0x3ce, 0x05);
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bus_space_write_1(*iot, *ioh, 0x3cf, 0x40);
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#define TEST_PATTERN 0xa5a5a5a5
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bus_space_write_4(*memt, *memh, 0x0, TEST_PATTERN);
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if (bus_space_read_4(*memt, *memh, 0x0) != TEST_PATTERN)
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{
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#ifdef DEBUG_ET4000
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printf("et4000: Video base write/read failed\n");
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#else
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et4k_stop(iot, ioh, &vgabase, &saved);
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return 0;
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#endif
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}
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bus_space_write_4(*memt, *memh, memsize - 4, TEST_PATTERN);
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if (bus_space_read_4(*memt, *memh, memsize - 4) != TEST_PATTERN)
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{
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#ifdef DEBUG_ET4000
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printf("et4000: Video top write/read failed\n");
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#else
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et4k_stop(iot, ioh, &vgabase, &saved);
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return 0;
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#endif
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}
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et4k_stop(iot, ioh, &vgabase, &saved);
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return 1;
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}
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static void
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et4k_vme_attach(device_t parent, device_t self, void *aux)
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{
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struct et4k_softc *sc = device_private(self);
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struct vme_attach_args *va = aux;
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bus_space_handle_t ioh;
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bus_space_handle_t memh;
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sc->sc_dev = self;
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printf("\n");
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if (bus_space_map(va->va_iot, va->va_iobase, va->va_iosize, 0, &ioh))
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panic("%s: cannot map io area", __func__);
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if (bus_space_map(va->va_memt, va->va_maddr, va->va_msize, 0, &memh))
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panic("%s: cannot map mem area", __func__);
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sc->sc_iot = va->va_iot;
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sc->sc_ioh = ioh;
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sc->sc_memt = va->va_memt;
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sc->sc_memh = memh;
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sc->sc_flags = 0;
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sc->sc_iobase = va->va_iobase;
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sc->sc_maddr = va->va_maddr;
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sc->sc_iosize = va->va_iosize;
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sc->sc_msize = va->va_msize;
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et4k_priv.regkva = (volatile void *)ioh;
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et4k_priv.memkva = (volatile void *)memh;
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et4k_priv.regsz = va->va_iosize;
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et4k_priv.memsz = va->va_msize;
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}
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int
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et4kopen(dev_t dev, int flags, int devtype, struct lwp *l)
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{
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struct et4k_softc *sc;
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sc = device_lookup_private(&et4k_cd, minor(dev));
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if (sc == NULL)
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return ENXIO;
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if (sc->sc_flags & ET_SC_FLAGS_INUSE)
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return EBUSY;
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sc->sc_flags |= ET_SC_FLAGS_INUSE;
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return 0;
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}
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int
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et4kclose(dev_t dev, int flags, int devtype, struct lwp *l)
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{
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struct et4k_softc *sc;
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/*
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* XXX: Should we reset to a default mode?
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*/
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sc = device_lookup_private(&et4k_cd, minor(dev));
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sc->sc_flags &= ~ET_SC_FLAGS_INUSE;
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return 0;
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}
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int
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et4kread(dev_t dev, struct uio *uio, int flags)
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{
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return EINVAL;
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}
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int
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et4kwrite(dev_t dev, struct uio *uio, int flags)
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{
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return EINVAL;
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}
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int
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et4kioctl(dev_t dev, u_long cmd, void *data, int flags, struct lwp *l)
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{
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struct grfinfo g_display;
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struct et4k_softc *sc;
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sc = device_lookup_private(&et4k_cd, minor(dev));
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switch (cmd) {
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case GRFIOCON:
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return 0;
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break;
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case GRFIOCOFF:
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return 0;
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break;
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case GRFIOCGINFO:
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g_display.gd_fbaddr = (void *) (sc->sc_maddr);
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g_display.gd_fbsize = sc->sc_msize;
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g_display.gd_linbase = FRAME_BASE;
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g_display.gd_regaddr = (void *) (sc->sc_iobase);
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g_display.gd_regsize = sc->sc_iosize;
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g_display.gd_vgaaddr = (void *) (sc->sc_maddr);
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g_display.gd_vgasize = VGA_MAPPABLE;
|
|
g_display.gd_vgabase = VGA_BASE;
|
|
g_display.gd_colors = 16;
|
|
g_display.gd_planes = 4;
|
|
g_display.gd_fbwidth = 640; /* XXX: should be 'unknown' */
|
|
g_display.gd_fbheight = 400; /* XXX: should be 'unknown' */
|
|
g_display.gd_fbx = 0;
|
|
g_display.gd_fby = 0;
|
|
g_display.gd_dwidth = 0;
|
|
g_display.gd_dheight = 0;
|
|
g_display.gd_dx = 0;
|
|
g_display.gd_dy = 0;
|
|
g_display.gd_bank_size = 0;
|
|
memcpy(data, (void *)&g_display, sizeof(struct grfinfo));
|
|
break;
|
|
case GRFIOCMAP:
|
|
return EINVAL;
|
|
break;
|
|
case GRFIOCUNMAP:
|
|
return EINVAL;
|
|
break;
|
|
default:
|
|
return EINVAL;
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
paddr_t
|
|
et4kmmap(dev_t dev, off_t offset, int prot)
|
|
{
|
|
struct et4k_softc *sc;
|
|
|
|
sc = device_lookup_private(&et4k_cd, minor(dev));
|
|
|
|
/*
|
|
* control registers
|
|
* mapped from offset 0x0 to REG_MAPPABLE
|
|
*/
|
|
if (offset >= 0 && offset <= sc->sc_iosize)
|
|
return m68k_btop(sc->sc_iobase + offset);
|
|
|
|
/*
|
|
* VGA memory
|
|
* mapped from offset 0xa0000 to 0xc0000
|
|
*/
|
|
if (offset >= VGA_BASE && offset < (VGA_MAPPABLE + VGA_BASE))
|
|
return m68k_btop(sc->sc_maddr + offset - VGA_BASE);
|
|
|
|
/*
|
|
* frame buffer
|
|
* mapped from offset 0x400000 to 0x4fffff
|
|
*/
|
|
if (offset >= FRAME_BASE && offset < sc->sc_msize + FRAME_BASE)
|
|
return m68k_btop(sc->sc_maddr + offset - FRAME_BASE);
|
|
|
|
return -1;
|
|
}
|
|
|
|
int
|
|
et4kon(dev_t dev)
|
|
{
|
|
struct et4k_softc *sc;
|
|
|
|
if (minor(dev) >= et4k_cd.cd_ndevs)
|
|
return ENXIO;
|
|
sc = device_lookup_private(&et4k_cd, minor(dev));
|
|
if (sc == NULL)
|
|
return ENXIO;
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
et4koff(dev_t dev)
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|