147 lines
6.3 KiB
C
147 lines
6.3 KiB
C
/* $NetBSD: sscom_reg.h,v 1.2 2014/04/14 21:16:15 reinoud Exp $ */
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/*
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* Copyright (c) 2002, 2003 Fujitsu Component Limited
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* Copyright (c) 2002, 2003 Genetec Corporation
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of The Fujitsu Component Limited nor the name of
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* Genetec corporation may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY FUJITSU COMPONENT LIMITED AND GENETEC
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* CORPORATION ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL FUJITSU COMPONENT LIMITED OR GENETEC
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* CORPORATION BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Register definitions for the Exynos[45] chipsets UARTs
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*/
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#ifndef _ARM_SAMSUNG_SSCOM_REG_H_
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#define _ARM_SAMSUNG_SSCOM_REG_H_
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#define SSCOM_ULCON 0x00 /* UART line control */
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#define ULCON_IR __BIT(6)
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#define ULCON_PARITY __BITS(5,3)
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#define ULCON_PARITY_NONE __SHIFTIN(0, ULCON_PARITY)
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#define ULCON_PARITY_ODD __SHIFTIN(4, ULCON_PARITY)
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#define ULCON_PARITY_EVEN __SHIFTIN(5, ULCON_PARITY)
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#define ULCON_PARITY_ONE __SHIFTIN(6, ULCON_PARITY)
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#define ULCON_PARITY_ZERO __SHIFTIN(7, ULCON_PARITY)
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#define ULCON_STOP __BIT(2)
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#define ULCON_LENGTH_5 0
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#define ULCON_LENGTH_6 1
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#define ULCON_LENGTH_7 2
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#define ULCON_LENGTH_8 3
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#define SSCOM_UCON 0x04 /* UART control */
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#define UCON_TXDMA_BRST __BITS(22,20)
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#define UCON_TXDMA_BRST_1 __SHIFTIN(0, UCON_TXDMA)
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#define UCON_TXDMA_BRST_4 __SHIFTIN(1, UCON_TXDMA)
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#define UCON_TXDMA_BRST_8 __SHIFTIN(2, UCON_TXDMA)
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#define UCON_TXDMA_BRST_16 __SHIFTIN(3, UCON_TXDMA)
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#define UCON_RXDMA_BRST __BITS(18,16)
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#define UCON_RXDMA_BRST_1 __SHIFTIN(0, UCON_RXDMA)
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#define UCON_RXDMA_BRST_4 __SHIFTIN(1, UCON_RXDMA)
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#define UCON_RXDMA_BRST_8 __SHIFTIN(2, UCON_RXDMA)
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#define UCON_RXDMA_BRST_16 __SHIFTIN(3, UCON_RXDMA)
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#define UCON_RXTO __BITS(15,12)
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#define UCON_RXTO_FIFO_EMPTY __BIT(11)
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#define UCON_RXTO_DMA_FSM_STOP __BIT(10)
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#define UCON_TXINT_TYPE __BIT(9) /* Tx interrupt. 0=pulse,1=level */
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#define UCON_TXINT_TYPE_LEVEL UCON_TXINT_TYPE /* 4412 mandatory */
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#define UCON_TXINT_TYPE_PULSE 0
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#define UCON_RXINT_TYPE __BIT(8) /* Rx interrupt */
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#define UCON_RXINT_TYPE_LEVEL UCON_RXINT_TYPE /* 4412 mandatory */
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#define UCON_RXINT_TYPE_PULSE __SHIFTIN(0,UCON_RXINT_TYPE)
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#define UCON_TOINT __BIT(7) /* Rx timeout interrupt */
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#define UCON_ERRINT __BIT(6) /* receive error interrupt */
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#define UCON_LOOP __BIT(5) /* loopback */
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#define UCON_SBREAK __BIT(4) /* send break */
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#define UCON_TXMODE __BITS(3,2)
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#define UCON_TXMODE_DISABLE __SHIFTIN(0, UCON_TXMODE)
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#define UCON_TXMODE_INT __SHIFTIN(1, UCON_TXMODE)
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#define UCON_TXMODE_DMA __SHIFTIN(2, UCON_TXMODE)
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#define UCON_TXMODE_MASK __SHIFTIN(3, UCON_TXMODE)
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#define UCON_RXMODE __BITS(1,0)
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#define UCON_RXMODE_DISABLE __SHIFTIN(1, UCON_RXMODE)
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#define UCON_RXMODE_INT __SHIFTIN(1, UCON_RXMODE)
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#define UCON_RXMODE_DMA __SHIFTIN(2, UCON_RXMODE)
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#define UCON_RXMODE_MASK __SHIFTIN(3, UCON_RXMODE)
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#define SSCOM_UFCON 0x08 /* FIFO control */
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#define UFCON_TXTRIGGER __BITS(10,8)
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#define UFCON_RXTRIGGER __BITS(6,4)
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#define UFCON_TXFIFO_RESET __BIT(2)
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#define UFCON_RXFIFO_RESET __BIT(1)
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#define UFCON_FIFO_ENABLE __BIT(0)
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#define SSCOM_UMCON 0x0c /* MODEM control */
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#define UMCON_RTSTRIGGER __BITS(7,5)
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#define UMCON_AFC __BIT(4)
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#define UMCON_MODEMINT_ENABLE __BIT(3)
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#define UMCON_RTS __BIT(0) /* Request to send */
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#define SSCOM_UTRSTAT 0x10 /* Status register */
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#define UTRSTAT_RXFIFOCNT __BITS(23,16)
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#define UTRSTAT_TXDMA_FSM __BITS(15,12)
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#define UTRSTAT_RXDMA_FSM __BITS(11,8)
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#define UTRSTAT_RXTIMEOUT __BIT(3)
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#define UTRSTAT_TXSHIFTER_EMPTY __BIT(2)
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#define UTRSTAT_TXEMPTY __BIT(1) /* TX fifo or buffer empty */
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#define UTRSTAT_RXREADY __BIT(0) /* RX fifo or buffer is not empty */
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#define SSCOM_UERSTAT 0x14 /* Error status register */
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#define UERSTAT_BREAK __BIT(3) /* Break signal */
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#define UERSTAT_FRAME __BIT(2) /* Frame error */
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#define UERSTAT_PARITY __BIT(1) /* Parity error */
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#define UERSTAT_OVERRUN __BIT(0) /* Overrun */
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#define UERSTAT_ALL_ERRORS (UERSTAT_OVERRUN|UERSTAT_BREAK|UERSTAT_FRAME|UERSTAT_PARITY)
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#define SSCOM_UFSTAT 0x18 /* Fifo status register */
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#define UFSTAT_TXFULL __BIT(24) /* Tx fifo full */
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#define UFSTAT_TXCOUNT __BITS(23,16) /* TX FIFO count */
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#define UFSTAT_RXERROR __BIT(9)
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#define UFSTAT_RXFULL __BIT(8) /* Rx fifo full */
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#define UFSTAT_RXCOUNT __BITS(7,0) /* RX FIFO count */
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#define SSCOM_UMSTAT 0x1c /* Modem status register */
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#define UMSTAT_DCTS __BIT(4)
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#define UMSTAT_CTS __BIT(0) /* Clear to send */
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#if _BYTE_ORDER == _LITTLE_ENDIAN
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#define SSCOM_UTXH 0x20 /* Transmit data register */
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#define SSCOM_URXH 0x24 /* Receive data register */
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#else
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#define SSCOM_UTXH 0x23 /* Transmit data register */
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#define SSCOM_URXH 0x27 /* Receive data register */
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#endif
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#define SSCOM_UBRDIV 0x28 /* baud-rate divisor [15:0] */
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#define SSCOM_UFRACVAL 0x2C /* baud-rate fraction [3:0] */
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/* Interrupt controller */
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#define SSCOM_UINTP 0x30 /* interrupt source */
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#define SSCOM_UINTSP 0x34 /* pending interrupts */
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#define SSCOM_UINTM 0x38 /* interrupt masking */
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#define UINT_MODEM __BIT(3)
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#define UINT_TXD __BIT(2)
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#define UINT_ERROR __BIT(1)
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#define UINT_RXD __BIT(0)
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#define SSCOM_SIZE 0x3C
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#endif /* _ARM_SAMSUNG_SSCOM_REG_H_ */
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