120 lines
4.0 KiB
C
120 lines
4.0 KiB
C
/* $NetBSD: imxssireg.h,v 1.1 2010/11/13 07:11:03 bsh Exp $ */
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/*
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* Copyright (c) 2009 Genetec Corporation. All rights reserved.
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* Written by Hashimoto Kenichi for Genetec Corporation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMXSSIREG_H
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#define _ARM_IMX_IMXSSIREG_H
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#define SSI_STX0 0x0000
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#define SSI_STX1 0x0004
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#define SSI_SRX0 0x0008
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#define SSI_SRX1 0x000C
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#define SSI_SCR 0x0010
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#define SCR_CLK_IST __BIT(9)
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#define SCR_TCH_EN __BIT(8)
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#define SCR_SYS_CLK_EN __BIT(7)
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#define SCR_I2SMODE_MASK ((0x3)<<5)
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#define SCR_I2SMODE(n) ((n)<<5)
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#define I2SMODE_NORMAL (0)
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#define I2SMODE_MASTER (1)
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#define I2SMODE_SLAVE (2)
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#define SCR_SYN __BIT(4)
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#define SCR_NET __BIT(3)
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#define SCR_RE __BIT(2)
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#define SCR_TE __BIT(1)
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#define SCR_SSIEN __BIT(0)
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#define SSI_SISR 0x0014
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#define SSI_SIER 0x0018
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#define SI_RDMAE __BIT(22)
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#define SI_RIE __BIT(21)
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#define SI_TDMAE __BIT(20)
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#define SI_TIE __BIT(19)
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#define SI_CMDAU_EN __BIT(18)
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#define SI_CMDDU_EN __BIT(17)
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#define SI_RXT_EN __BIT(16)
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#define SI_RDR1_EN __BIT(15)
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#define SI_RDR0_EN __BIT(14)
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#define SI_TDE1_EN __BIT(13)
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#define SI_TDE0_EN __BIT(12)
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#define SI_ROE1_EN __BIT(11)
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#define SI_ROE0_EN __BIT(10)
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#define SI_TUE1_EN __BIT(9)
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#define SI_TUE0_EN __BIT(8)
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#define SI_RFS_EN __BIT(7)
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#define SI_TFS_EN __BIT(6)
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#define SI_RLS_EN __BIT(5)
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#define SI_TLS_EN __BIT(4)
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#define SI_RFF1_EN __BIT(3)
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#define SI_RFF0_EN __BIT(2)
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#define SI_TFE1_EN __BIT(1)
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#define SI_TFE0_EN __BIT(0)
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#define SSI_STCR 0x001C
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#define SSI_SRCR 0x0020
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#define CR_XEX __BIT(10)
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#define CR_XBIT __BIT(9)
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#define CR_FEN1 __BIT(8)
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#define CR_FEN0 __BIT(7)
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#define CR_FDIR __BIT(6)
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#define CR_XDIR __BIT(5)
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#define CR_SHFD __BIT(4)
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#define CR_SHFD_MSB (0<<4)
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#define CR_SHFD_LSB CR_SHFD
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#define CR_SCKP __BIT(3)
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#define CR_FSI __BIT(2)
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#define CR_FSL __BIT(1)
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#define CR_EFS __BIT(0)
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#define SSI_STCCR 0x0024
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#define SSI_SRCCR 0x0028
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#define WL_SHIFT 13
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#define WL_MASK (0xf << 13)
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#define DC_SHIFT 8
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#define DC_MASK (0xf << 8)
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#define SSI_SFCSR 0x002C
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#define SFCSR_RFCNT1_MASK (0xf << 28)
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#define SFCSR_TFCNT1_MASK (0xf << 24)
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#define SFCSR_RFWM1_MASK (0xf << 20)
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#define SFCSR_TFWM1_MASK (0xf << 16)
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#define SFCSR_RFCNT0_MASK (0xf << 12)
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#define SFCSR_TFCNT0_MASK (0xf << 8)
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#define SFCSR_RFWM0_MASK (0xf << 4)
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#define SFCSR_TFWM0_MASK (0xf << 0)
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#define SFCSR_RFWM1(x) (((x) & 0xf) << 20)
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#define SFCSR_TFWM1(x) (((x) & 0xf) << 16)
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#define SFCSR_RFWM0(x) (((x) & 0xf) << 4)
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#define SFCSR_TFWM0(x) (((x) & 0xf) << 0)
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#define SSI_SACNT 0x0038
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#define SSI_SACSDD 0x003C
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#define SSI_SACDAT 0x0040
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#define SSI_SATAG 0x0044
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#define SSI_STMSK 0x0048
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#define SSI_SRMSK 0x004C
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#define SSI_SIZE 0x100
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#endif /* _ARM_IMX_IMXSSIREG_H */
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