425 lines
14 KiB
C
425 lines
14 KiB
C
/* $NetBSD: imx51reg.h,v 1.7 2015/05/07 04:37:29 hkenken Exp $ */
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/*-
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* Copyright (c) 2007 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_IMX_IMX51REG_H_
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#define _ARM_IMX_IMX51REG_H_
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#ifdef IMX50
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#define TZIC_BASE 0x0fffc000
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#define APB_BASE 0x40000000
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#define AIPSTZ1_BASE 0x50000000
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#define AIPSTZ2_BASE 0x60000000
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#define CSD0DDR_BASE 0x70000000
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#else
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#define TZIC_BASE 0xe0000000
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#define AIPSTZ1_BASE 0x70000000
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#define AIPSTZ2_BASE 0x80000000
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#define CSD0DDR_BASE 0x90000000
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#define CSD1DDR_BASE 0xa0000000
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#define CSDDDR_SIZE 0x10000000 /* 256MiB */
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#define CS0_BASE 0xb0000000
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#define CS0_SIZE 0x08000000 /* 128MiB */
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#define CS1_BASE 0xb8000000
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#define CS1_SIZE 0x08000000 /* 128MiB */
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#define CS2_BASE 0xc0000000
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#define CS2_SIZE 0x08000000 /* 128MiB */
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#define CS3_BASE 0xc8000000
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#define CS3_SIZE 0x04000000 /* 64MiB */
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#define CS4_BASE 0xcc000000
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#define CS4_SIZE 0x02000000 /* 32MiB */
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#define CS5_BASE 0xcefe0000
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#define CS5_SIZE 0x00010000 /* 32MiB */
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#define NAND_FLASH_BASE 0xcfff0000 /* internal buffer */
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#define NAND_FLASH_SIZE 0x00010000
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#define GPU2D_BASE 0xd0000000
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#define GPU2D_SIZE 0x10000000
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#endif
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#define BOOTROM_BASE 0x00000000
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#define BOOTROM_SIZE 0x9000
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#define SCCRAM_BASE 0x1ffe0000
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#define SCCRAM_SIZE 0x20000
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#define GPUMEM_BASE 0x20000000
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#define GPUMEM_SIZE 0x20000
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#define GPU_BASE 0x30000000
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#define GPU_SIZE 0x10000000
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#ifdef IMX50
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#define EPDC_BASE (APB_BASE + 0x01010000)
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#define EPDC_SIZE 0x2000
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#endif
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/* Image Prossasing Unit */
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#define IPU_BASE 0x40000000
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#define IPU_CM_BASE (IPU_BASE + 0x1e000000)
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#define IPU_CM_SIZE 0x8000
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#define IPU_IDMAC_BASE (IPU_BASE + 0x1e008000)
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#define IPU_IDMAC_SIZE 0x8000
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#define IPU_DP_BASE (IPU_BASE + 0x1e018000)
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#define IPU_DP_SIZE 0x8000
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#define IPU_IC_BASE (IPU_BASE + 0x1e020000)
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#define IPU_IC_SIZE 0x8000
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#define IPU_IRT_BASE (IPU_BASE + 0x1e028000)
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#define IPU_IRT_SIZE 0x8000
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#define IPU_CSI0_BASE (IPU_BASE + 0x1e030000)
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#define IPU_CSI0_SIZE 0x8000
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#define IPU_CSI1_BASE (IPU_BASE + 0x1e038000)
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#define IPU_CSI1_SIZE 0x8000
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#define IPU_DI0_BASE (IPU_BASE + 0x1e040000)
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#define IPU_DI0_SIZE 0x8000
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#define IPU_DI1_BASE (IPU_BASE + 0x1e048000)
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#define IPU_DI1_SIZE 0x8000
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#define IPU_SMFC_BASE (IPU_BASE + 0x1e050000)
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#define IPU_SMFC_SIZE 0x8000
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#define IPU_DC_BASE (IPU_BASE + 0x1e058000)
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#define IPU_DC_SIZE 0x8000
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#define IPU_DMFC_BASE (IPU_BASE + 0x1e060000)
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#define IPU_DMFC_SIZE 0x8000
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#define IPU_VDI_BASE (IPU_BASE + 0x1e068000)
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#define IPU_VDI_SIZE 0x8000
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#define IPU_CPMEM_BASE (IPU_BASE + 0x1f000000)
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#define IPU_CPMEM_SIZE 0x20000
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#define IPU_LUT_BASE (IPU_BASE + 0x1f020000)
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#define IPU_LUT_SIZE 0x20000
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#define IPU_SRM_BASE (IPU_BASE + 0x1f040000)
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#define IPU_SRM_SIZE 0x20000
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#define IPU_TPM_BASE (IPU_BASE + 0x1f060000)
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#define IPU_TPM_SIZE 0x20000
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#define IPU_DCTMPL_BASE (IPU_BASE + 0x1f080000)
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#define IPU_DCTMPL_SIZE 0x20000
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#define DEBUGROM_BASE 0x60000000
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#define DEBUGROM_SIZE 0x1000
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#define ESDHC1_BASE (AIPSTZ1_BASE + 0x00004000)
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#define ESDHC2_BASE (AIPSTZ1_BASE + 0x00008000)
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#define ESDHC3_BASE (AIPSTZ1_BASE + 0x00020000)
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#define ESDHC4_BASE (AIPSTZ1_BASE + 0x00024000)
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#define ESDHC_SIZE 0x4000
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#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
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#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
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#define UART1_BASE (AIPSTZ1_BASE + 0x03fbc000)
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#define UART2_BASE (AIPSTZ1_BASE + 0x03fc0000)
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#define UART3_BASE (AIPSTZ1_BASE + 0x0000c000)
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/* register definitions in imxuartreg.h */
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#define CCMC_BASE (AIPSTZ1_BASE + 0x03fd4000)
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#define ECSPI1_BASE (AIPSTZ1_BASE + 0x00010000)
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#define ECSPI2_BASE (AIPSTZ2_BASE + 0x03fac000)
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#define ECSPI_SIZE 0x4000
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#define SSI1_BASE (AIPSTZ2_BASE + 0x03fcc000)
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#define SSI2_BASE (AIPSTZ1_BASE + 0x00014000)
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#define SSI3_BASE (AIPSTZ2_BASE + 0x03fe8000)
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/* register definitions in imxssireg.h */
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#define SPDIF_BASE (AIPSTZ1_BASE + 0x00028000)
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#define SPDIF_SIZE 0x4000
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#define PATA_UDMA_BASE (AIPSTZ1_BASE + 0x00030000)
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#define PATA_UDMA_SIZE 0x4000
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#define PATA_PIO_BASE (AIPSTZ2_BASE + 0x03fe0000)
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#define PATA_PIO_SIZE 0x4000
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#define SLM_BASE (AIPSTZ1_BASE + 0x00034000)
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#define SLM_SIZE 0x4000
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#ifdef IMX50
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#define I2C3_BASE (AIPSTZ1_BASE + 0x00038000)
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#define I2C3_SIZE 0x4000
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#else
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#define HSI2C_BASE (AIPSTZ1_BASE + 0x00038000)
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#define HSI2C_SIZE 0x4000
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#endif
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#define SPBA_BASE (AIPSTZ1_BASE + 0x0003c000)
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#define SPBA_SIZE 0x4000
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#define USBOH3_BASE (AIPSTZ1_BASE + 0x03f80000)
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#define USBOH3_PL301_BASE (AIPSTZ1_BASE + 0x03fc4000)
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#define USBOH3_EHCI_SIZE 0x200
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#define USBOH3_OTG 0x000
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#define USBOH3_EHCI(n) (USBOH3_EHCI_SIZE*(n)) /* n=1,2,3 */
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/* USB_CTRL register */
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#define USBOH3_USBCTRL 0x800
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#define USBCTRL_OWIR __BIT(31) /* OTG Wakeup interrupt request */
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#define USBCTRL_OSIC __BITS(29,30) /* OTG Serial interface configuration */
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#define USBCTRL_OUIE __BIT(28) /* OTG Wake-up interrupt enable */
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#define USBCTRL_OBPAL __BITS(25,26) /* OTG Bypass value */
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#define USBCTRL_OPM __BIT(24) /* OTG Power Mask */
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#define USBCTRL_ICVOL __BIT(23) /* Host1 IC_USB voltage status */
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#define USBCTRL_ICTPIE __BIT(19) /* IC USB TP interrupt enable */
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#define USBCTRL_UBPCKE __BIT(18) /* Bypass clock enable */
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#define USBCTRL_H1TCKOEN __BIT(17) /* Host1 ULPO PHY clock enable */
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#define USBCTRL_ICTPC __BIT(16) /* Clear IC TP interrupt flag */
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#define USBCTRL_H1WIR __BIT(15) /* Host1 wakeup interrupt request */
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#define USBCTRL_H1SIC __BITS(13,14) /* Host1 serial interface config */
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#define USBCTRL_H1UIE __BIT(12) /* Host1 ILPI interrupt enable */
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#define USBCTRL_H1WIE __BIT(11) /* Host1 wakeup interrupt enable */
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#define USBCTRL_H1BPVAL __BITS(9,10) /* Host1 bypass value */
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#define USBCTRL_H1PM __BIT(8) /* Host1 power mask */
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#define USBCTRL_OHSTLL __BIT(7) /* OTG ULPI TLL enable */
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#define USBCTRL_H1HSTLL __BIT(6) /* Host1 ULPI TLL enable */
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#define USBCTRL_H1DISFSTTL __BIT(4) /* Host1 serial TLL disable */
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#define USBCTRL_OTCKOEN __BIT(1) /* OTG ULPI PHY clock enable */
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#define USBCTRL_BPE __BIT(0) /* Bypass enable */
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#define USBOH3_OTGMIRROR 0x804
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#define USBOH3_PHYCTRL0 0x808
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#define PHYCTRL0_VLOAD __BIT(31)
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#define PHYCTRL0_VCONTROL __BITS(27,30)
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#define PHYCTRL0_CONF2 __BIT(26)
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#define PHYCTRL0_CONF3 __BIT(25)
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#define PHYCTRL0_CHGRDETEN __BIT(24)
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#define PHYCTRL0_CHGRDETON __BIT(23)
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#define PHYCTRL0_VSTATUS __BITS(15,22)
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#define PHYCTRL0_SUSPENDM __BIT(12)
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#define PHYCTRL0_RESET __BIT(11)
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#define PHYCTRL0_UTMI_ON_CLOCK __BIT(10)
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#define PHYCTRL0_OTG_OVER_CUR_POL __BIT(9)
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#define PHYCTRL0_OTG_OVER_CUR_DIS __BIT(8)
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#define PHYCTRL0_OTG_XCVR_CLK_SEL __BIT(7)
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#define PHYCTRL0_H1_OVER_CUR_POL __BIT(6)
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#define PHYCTRL0_H1_OVER_CUR_DIS __BIT(5)
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#define PHYCTRL0_H1_XCVR_CLK_SEL __BIT(4)
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#define PHYCTRL0_PWR_POL __BIT(3)
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#define PHYCTRL0_CHRGDET __BIT(2)
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#define PHYCTRL0_CHRGDET_INT_EN __BIT(1)
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#define PHYCTRL0_CHRGDET_INT_FLG __BIT(0)
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#define USBOH3_PHYCTRL1 0x80c
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#define PHYCTRL1_PLLDIVVALUE_MASK __BITS(0,1)
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#define PHYCTRL1_PLLDIVVALUE_19MHZ 0 /* 19.2MHz */
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#define PHYCTRL1_PLLDIVVALUE_24MHZ 1
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#define PHYCTRL1_PLLDIVVALUE_26MHZ 2
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#define PHYCTRL1_PLLDIVVALUE_27MHZ 3
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#define USBOH3_USBCTRL1 0x810
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#define USBCTRL1_UH3_EXT_CLK_EN __BIT(27)
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#define USBCTRL1_UH2_EXT_CLK_EN __BIT(26)
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#define USBCTRL1_UH1_EXT_CLK_EN __BIT(25)
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#define USBCTRL1_OTG_EXT_CLK_EN __BIT(24)
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#define USBOH3_USBCTRL2 0x814
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#define USBOH3_USBCTRL3 0x818
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#define USBOH3_UH1_PHY_CTRL_0 0x81c
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#define USBOH3_UH1_PHY_CTRL_1 0x820
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#define USBOH3_USB_CLKONOFF_CTRL 0x824
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#define USB_CLKONOFF_CTRL_H1_AHBCLK_OFF __BIT(18)
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#define USB_CLKONOFF_CTRL_OTG_AHBCLK_OFF __BIT(17)
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#define USBOH3_SIZE 0x4000
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/* GPIO module */
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#define GPIO_BASE(n) \
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(AIPSTZ1_BASE + (((n) <= 4) ? \
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0x03f84000 + 0x4000 * ((n) - 1) : \
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0x03fdc000 + 0x4000 * ((n) - 5)))
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#define GPIO1_BASE GPIO_BASE(1)
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#define GPIO2_BASE GPIO_BASE(2)
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#define GPIO3_BASE GPIO_BASE(3)
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#define GPIO4_BASE GPIO_BASE(4)
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#define GPIO5_BASE GPIO_BASE(5)
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#define GPIO6_BASE GPIO_BASE(6)
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#ifdef IMX50
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#define GPIO_NGROUPS 6
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#else
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#define GPIO_NGROUPS 4
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#endif
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#define KPP_BASE (AIPSTZ1_BASE + 0x03f94000)
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/* register definitions in imxkppreg.h */
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#define WDOG1_BASE (AIPSTZ1_BASE + 0x03f98000)
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#define WDOG2_BASE (AIPSTZ1_BASE + 0x03f9c000)
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#define WDOG_SIZE 0x4000
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#define GPT_BASE (AIPSTZ1_BASE + 0x03fa0000)
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#define GPT_SIZE 0x4000
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#define SRTC_BASE (AIPSTZ1_BASE + 0x03fa4000)
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#define SRTC_SIZE 0x4000
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/* IO multiplexor */
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#define IOMUXC_BASE (AIPSTZ1_BASE + 0x03fa8000)
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#define IOMUXC_SIZE 0x4000
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#define IOMUXC_MUX_CTL 0x001c /* multiprex control */
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#define IOMUX_CONFIG_SION __BIT(4)
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#define IOMUX_CONFIG_ALT0 (0)
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#define IOMUX_CONFIG_ALT1 (1)
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#define IOMUX_CONFIG_ALT2 (2)
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#define IOMUX_CONFIG_ALT3 (3)
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#define IOMUX_CONFIG_ALT4 (4)
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#define IOMUX_CONFIG_ALT5 (5)
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#define IOMUX_CONFIG_ALT6 (6)
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#define IOMUX_CONFIG_ALT7 (7)
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#define IOMUXC_PAD_CTL 0x03f0 /* pad control */
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#define PAD_CTL_HVE __BIT(13)
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#define PAD_CTL_DDR_INPUT __BIT(9)
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#define PAD_CTL_HYS __BIT(8)
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#define PAD_CTL_PKE __BIT(7)
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#define PAD_CTL_PUE __BIT(6)
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#define PAD_CTL_PULL (PAD_CTL_PKE|PAD_CTL_PUE)
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#define PAD_CTL_KEEPER (PAD_CTL_PKE|0)
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#define PAD_CTL_PUS_MASK __BITS(5, 4)
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#define PAD_CTL_PUS_100K_PD __SHIFTIN(0x0, PAD_CTL_PUS_MASK)
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#define PAD_CTL_PUS_47K_PU __SHIFTIN(0x1, PAD_CTL_PUS_MASK)
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#define PAD_CTL_PUS_100K_PU __SHIFTIN(0x2, PAD_CTL_PUS_MASK)
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#define PAD_CTL_PUS_22K_PU __SHIFTIN(0x3, PAD_CTL_PUS_MASK)
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#define PAD_CTL_ODE __BIT(3) /* opendrain */
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#define PAD_CTL_DSE_MASK __BITS(2, 1)
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#define PAD_CTL_DSE_LOW __SHIFTIN(0x0, PAD_CTL_DSE_MASK)
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#define PAD_CTL_DSE_MID __SHIFTIN(0x1, PAD_CTL_DSE_MASK)
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#define PAD_CTL_DSE_HIGH __SHIFTIN(0x2, PAD_CTL_DSE_MASK)
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#define PAD_CTL_DSE_MAX __SHIFTIN(0x3, PAD_CTL_DSE_MASK)
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#define PAD_CTL_SRE __BIT(0)
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#define IOMUXC_INPUT_CTL 0x08c4 /* input control */
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#define INPUT_DAISY_0 0
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#define INPUT_DAISY_1 1
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#define INPUT_DAISY_2 2
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#define INPUT_DAISY_3 3
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#define INPUT_DAISY_4 4
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#define INPUT_DAISY_5 5
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#define INPUT_DAISY_6 6
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#define INPUT_DAISY_7 7
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/*
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* IOMUX index
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*/
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#define IOMUX_PIN_TO_MUX_ADDRESS(pin) (((pin) >> 16) & 0xffff)
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#define IOMUX_PIN_TO_PAD_ADDRESS(pin) (((pin) >> 0) & 0xffff)
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#define IOMUX_PIN(mux_adr, pad_adr) \
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(((mux_adr) << 16) | (((pad_adr) << 0)))
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#define IOMUX_MUX_NONE 0xffff
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#define IOMUX_PAD_NONE 0xffff
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/* EPIT */
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#define EPIT1_BASE (AIPSTZ1_BASE + 0x03FAC000)
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#define EPIT2_BASE (AIPSTZ1_BASE + 0x03FB0000)
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/* register definitions in imxepitreg.h */
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#define PWM1_BASE (AIPSTZ1_BASE + 0x03fb4000)
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#define PWM2_BASE (AIPSTZ1_BASE + 0x03fb8000)
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#define PWM_SIZE 0x4000
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#define SRC_BASE (AIPSTZ1_BASE + 0x03fd0000)
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#define SRC_SIZE 0x4000
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#define CCM_BASE (AIPSTZ1_BASE + 0x03fd4000)
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#define CCM_SIZE 0x4000
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#define GPC_BASE (AIPSTZ1_BASE + 0x03fd8000)
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#define GPC_SIZE 0x4000
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#define AHBMAX_BASE (AIPSTZ2_BASE + 0x03f94000)
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#define AHBMAX_SIZE 0x4000
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#define IIM_BASE (AIPSTZ2_BASE + 0x03f98000)
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#define IIM_SIZE 0x4000
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#define CSU_BASE (AIPSTZ2_BASE + 0x03f9c000)
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#define CSU_SIZE 0x4000
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#define OWIRE_BASE (AIPSTZ2_BASE + 0x03fa4000)
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#define OWIRE_SIZE 0x4000
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#define FIRI_BASE (AIPSTZ2_BASE + 0x03fa8000)
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#define FIRI_SIZE 0x4000
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#define SDMA_BASE (AIPSTZ2_BASE + 0x03fb0000)
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#define SDMA_SIZE 0x4000
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/* see imxsdmareg.h for register definitions */
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#define SCC_BASE (AIPSTZ2_BASE + 0x03fb4000)
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#define SCC_SIZE 0x4000
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#define ROMCP_BASE (AIPSTZ2_BASE + 0x03fb8000)
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#define ROMCP_SIZE 0x4000
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#define RTIC_BASE (AIPSTZ2_BASE + 0x03fbc000)
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#define RTIC_SIZE 0x4000
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#define CSPI_BASE (AIPSTZ2_BASE + 0x03fc0000)
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#define CSPI_SIZE 0x4000
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#define I2C1_BASE (AIPSTZ2_BASE + 0x03fc8000)
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#define I2C2_BASE (AIPSTZ2_BASE + 0x03fc4000)
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#define I2C_SIZE 0x4000
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#define AUDMUX_BASE (AIPSTZ2_BASE + 0x03fd0000)
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#define AUDMUX_SIZE 0x4000
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#define AUDMUX_PTCR(n) ((n - 1) * 0x8)
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#define PTCR_TFSDIR (1 << 31)
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#define PTCR_TFSEL(x) (((x) & 0x7) << 27)
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#define PTCR_TCLKDIR (1 << 26)
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#define PTCR_TCSEL(x) (((x) & 0x7) << 22)
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#define PTCR_RFSDIR (1 << 21)
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#define PTCR_RFSEL(x) (((x) & 0x7) << 17)
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#define PTCR_RCLKDIR (1 << 16)
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#define PTCR_RCSEL(x) (((x) & 0x7) << 12)
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#define PTCR_SYN (1 << 11)
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#define AUDMUX_PDCR(n) ((n - 1) * 0x8 + 0x4)
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#define PDCR_RXDSEL(x) (((x) & 0x7) << 13)
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#define PDCR_TXRXEN (1 << 12)
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#define PDCR_MODE(x) (((x) & 0x3) << 8)
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#define PDCR_INMMASK(x) (((x) & 0xff) << 0)
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#define AUDMUX_CNMCR 0x38
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#define EMI_BASE (AIPSTZ2_BASE + 0x03fd8000)
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#define EMI_SIZE 0x4000
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#define SIM_BASE (AIPSTZ2_BASE + 0x03fe4000)
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#define SIM_SIZE 0x4000
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#define FEC_BASE (AIPSTZ2_BASE + 0x03fec000)
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#define FEC_SIZE 0x4000
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#define TVE_BASE (AIPSTZ2_BASE + 0x03ff0000)
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#define TVE_SIZE 0x4000
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#define VPU_BASE (AIPSTZ2_BASE + 0x03ff4000)
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#define VPU_SIZE 0x4000
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#define SAHARA_BASE (AIPSTZ2_BASE + 0x03ff8000)
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#define SAHARA_SIZE 0x4000
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#define DPLL_BASE(n) ((AIPSTZ2_BASE + 0x03F80000 + (0x4000 * ((n)-1))))
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#define DPLL_SIZE 0x4000
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#endif /* _ARM_IMX_IMX51REG_H_ */
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