118 lines
3.9 KiB
C
118 lines
3.9 KiB
C
/* $NetBSD: g2_reg.h,v 1.1 2013/02/19 16:07:23 matt Exp $ */
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/*-
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* Copyright (c) 2013 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Matt Thomas of 3am Software Foundry.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _ARM_CORTINA_G2_REG_H_
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#define _ARM_CORTINA_G2_REG_H_
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#define G2_PERIPH_PBASE 0xf0000000
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#define G2_PERIPH_SIZE 0x00100000
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#define G2_SDRAM_PBASE 0xf0500000
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#define G2_TRNG_PBASE 0xf0600000
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#define G2_AHBAXI_PBASE 0xf4000000
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#define G2_EHCI_PBASE 0xf4000000
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#define G2_OHCI_PBASE 0xf4040000
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#define G2_USBD_PBASE 0xf4080000
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#define G2_SDC_PBASE 0xf40c0000
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#define G2_AHCI_PBASE 0xf4100000
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#define G2_RTC_PBASE 0xf4200000
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#define G2_CIR_PWRCTRL_PBASE 0xf4210000
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#define G2_SPDIF_PBASE 0xf4270000
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#define G2_ROMOTP_PBASE 0xf5008800
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#define G2_CRYPTO_PBASE 0xf6600000
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#define G2_CRYPTO_SIZE 0x00300000
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#define G2_RECIRC_TOP 0xf6800000
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#define G2_ARMCORE_PBASE 0xf8000000
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#define G2_ARMCORE_SIZE 0x00002000
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#define G2_PCIE0_PBASE 0x80000000
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#define G2_PCIE1_PBASE 0xa0000000
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#define G2_PCIE2_PBASE 0xc0000000
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#defien G2_PCIE_MEM_SIZE 0x20000000
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#define G2_UART0_BASE 0x70110
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#define G2_UART1_BASE 0x70140
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#define G2_UART2_BASE 0x70170
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#define G2_UART3_BASE 0x701a0
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#define G2_UART_CFG 0x00
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#define G2_UART_FC 0x04
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#define G2_UART_RXSAMPLE 0x08
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#define G2_UART_TXDAT 0x10
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#define G2_UART_RXDAT 0x14
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#define G2_UART_INFO 0x18
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#define G2_UART_IE0 0x1c
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#define G2_UART_IE1 0x20
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#define G2_UART_INT0 0x24
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#define G2_UART_INT1 0x28
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#define G2_UART_STAT 0x2c
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#define UART_CFG_BAUD_COUNT __BITS(31,8)
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#define UART_CFG_UART_EN __BIT(7)
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#define UART_CFG_RX_SM_EN __BIT(6)
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#define UART_CFG_TX_SM_EN __BIT(5)
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#define UART_CFG_PARITY_EN __BIT(4)
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#define UART_CFG_EVEN_EN __BIT(3)
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#define UART_CFG_STOP_2BIT __BIT(2)
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#define UART_CFG_CHAR_CNT __BITS(1,0)
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#define UART_FC_NO_RTS __BIT(10)
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#define UART_FC_INV_RTS __BIT(9)
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#define UART_FC_CTS_REG __BIT(8)
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#define UART_FC_NO_CTS __BIT(7)
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#define UART_FC_INV_CTS __BIT(6)
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#define UART_FC_RX_WM __BITS(5,0)
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#define UART_RXSAMPLE_CENTER __BITS(23,0)
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#define UART_RXDAT_VALID __BIT(8)
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#define UART_RXDAT_DATA __BITS(7,0)
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#define UART_INFO_TXFIFO_EMPTY __BIT(3)
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#define UART_INFO_TXFIFO_FULL __BIT(2)
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#define UART_INFO_RXFIFO_EMPTY __BIT(1)
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#define UART_INFO_RXFIFO_FULL __BIT(0)
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#define UART_IE_RXFIFO_NONEMPTY _BIT(6)
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#define UART_IE_TXFIFO_EMPTY _BIT(5)
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#define UART_IE_RXFIFO_UNDERRUN _BIT(4)
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#define UART_IE_RXFIFO_OVERRUN _BIT(3)
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#define UART_IE_RXPARITY_ERR _BIT(2)
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#define UART_IE_RXSTOP_ERR _BIT(1)
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#define UART_IE_TXFIFO_OVERRUN _BIT(0)
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#endif /* _ARM_CORTINA_G2_REG_H_ */
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