573 lines
18 KiB
C
573 lines
18 KiB
C
/* $NetBSD: if_fxp_pci.c,v 1.86 2021/05/08 00:27:02 thorpej Exp $ */
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/*-
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* Copyright (c) 1997, 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI bus front-end for the Intel i82557 fast Ethernet controller
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* driver. Works with Intel Etherexpress Pro 10+, 100B, 100+ cards.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: if_fxp_pci.c,v 1.86 2021/05/08 00:27:02 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <machine/endian.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#include <sys/bus.h>
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#include <sys/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/ic/i82557reg.h>
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#include <dev/ic/i82557var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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struct fxp_pci_softc {
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struct fxp_softc psc_fxp;
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pci_chipset_tag_t psc_pc; /* pci chipset tag */
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pcireg_t psc_regs[0x20>>2]; /* saved PCI config regs (sparse) */
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pcitag_t psc_tag; /* pci register tag */
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struct pci_conf_state psc_pciconf; /* standard PCI configuration regs */
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};
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static int fxp_pci_match(device_t, cfdata_t, void *);
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static void fxp_pci_attach(device_t, device_t, void *);
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static int fxp_pci_detach(device_t, int);
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static int fxp_pci_enable(struct fxp_softc *);
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static void fxp_pci_confreg_restore(struct fxp_pci_softc *psc);
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static bool fxp_pci_resume(device_t dv, const pmf_qual_t *);
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CFATTACH_DECL3_NEW(fxp_pci, sizeof(struct fxp_pci_softc),
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fxp_pci_match, fxp_pci_attach, fxp_pci_detach, NULL, NULL,
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null_childdetached, DVF_DETACH_SHUTDOWN);
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static const struct device_compatible_entry compat_data[] = {
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82552),
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.data = "Intel i82552 10/100 Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_8255X),
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.data = "Intel i8255x Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82559ER),
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.data = "Intel i82559ER Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_IN_BUSINESS),
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.data = "Intel InBusiness Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100),
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.data = "Intel PRO/100 Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_0),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_1),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_2),
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.data = "Intel PRO/100 VE Network Controller with 82562ET/EZ PHY" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_3),
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.data = "Intel PRO/100 VE Network Controller with 82562ET/EZ (CNR) PHY" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_4),
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.data = "Intel PRO/100 VE (MOB) Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_5),
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.data = "Intel PRO/100 VE (LOM) Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_6),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_7),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_8),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_9),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_10),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VE_11),
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.data = "Intel PRO/100 VE Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_0),
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.data = "Intel PRO/100 VM Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_1),
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.data = "Intel PRO/100 VM Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_2),
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.data = "Intel PRO/100 VM Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_3),
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.data = "Intel PRO/100 VM Network Controller with 82562EM/EX PHY" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_4),
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.data = "Intel PRO/100 VM Network Controller with 82562EM/EX (CNR) PHY" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_5),
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.data = "Intel PRO/100 VM (MOB) Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_6),
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.data = "Intel PRO/100 VM Network Controller with 82562ET/EZ PHY" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_7),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_8),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_9),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_10),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_11),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_12),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_13),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_14),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_15),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_VM_16),
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.data = "Intel PRO/100 VM Network Connection" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_PRO_100_M),
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.data = "Intel PRO/100 M Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801BA_LAN),
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.data = "Intel i82562 Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LAN_1),
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.data = "Intel i82801E Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801E_LAN_2),
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.data = "Intel i82801E Ethernet" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801EB_LAN),
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.data = "Intel 82801EB/ER (ICH5) Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LAN),
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.data = "Intel i82801FB LAN Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801FB_LAN_2),
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.data = "Intel i82801FB LAN Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801G_LAN),
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.data = "Intel 82801GB/GR (ICH7) Network Controller" },
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{ .id = PCI_ID_CODE(PCI_VENDOR_INTEL, PCI_PRODUCT_INTEL_82801GB_LAN),
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.data = "Intel 82801GB 10/100 Network Controller" },
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PCI_COMPAT_EOL
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};
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static int
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fxp_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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return pci_compatible_match(pa, compat_data);
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}
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/*
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* On resume : (XXX it is necessary with new pmf framework ?)
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* Restore PCI configuration registers that may have been clobbered.
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* This is necessary due to bugs on the Sony VAIO Z505-series on-board
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* ethernet, after an APM suspend/resume, as well as after an ACPI
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* D3->D0 transition. We call this function from a power hook after
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* APM resume events, as well as after the ACPI D3->D0 transition.
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*/
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static void
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fxp_pci_confreg_restore(struct fxp_pci_softc *psc)
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{
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pcireg_t reg;
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#if 0
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/*
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* Check to see if the command register is blank -- if so, then
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* we'll assume that all the clobberable-registers have been
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* clobbered.
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*/
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/*
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* In general, the above metric is accurate. Unfortunately,
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* it is inaccurate across a hibernation. Ideally APM/ACPI
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* code should take note of hibernation events and execute
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* a hibernation wakeup hook, but at present a hibernation wake
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* is indistinguishable from a suspend wake.
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*/
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if (((reg = pci_conf_read(psc->psc_pc, psc->psc_tag,
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PCI_COMMAND_STATUS_REG)) & 0xffff) != 0)
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return;
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#else
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reg = pci_conf_read(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG);
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#endif
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_COMMAND_STATUS_REG,
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(reg & 0xffff0000) |
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(psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] & 0xffff));
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_BHLC_REG,
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psc->psc_regs[PCI_BHLC_REG>>2]);
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x0,
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psc->psc_regs[(PCI_MAPREG_START+0x0)>>2]);
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x4,
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psc->psc_regs[(PCI_MAPREG_START+0x4)>>2]);
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pci_conf_write(psc->psc_pc, psc->psc_tag, PCI_MAPREG_START+0x8,
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psc->psc_regs[(PCI_MAPREG_START+0x8)>>2]);
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}
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static bool
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fxp_pci_resume(device_t dv, const pmf_qual_t *qual)
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{
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struct fxp_pci_softc *psc = device_private(dv);
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fxp_pci_confreg_restore(psc);
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return true;
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}
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static int
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fxp_pci_detach(device_t self, int flags)
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{
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struct fxp_pci_softc *psc = device_private(self);
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struct fxp_softc *sc = &psc->psc_fxp;
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int error;
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/* Finish off the attach. */
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if ((error = fxp_detach(sc, flags)) != 0)
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return error;
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pmf_device_deregister(self);
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pci_intr_disestablish(psc->psc_pc, sc->sc_ih);
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bus_space_unmap(sc->sc_st, sc->sc_sh, sc->sc_size);
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return 0;
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}
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static void
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fxp_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct fxp_pci_softc *psc = device_private(self);
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struct fxp_softc *sc = &psc->psc_fxp;
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const struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pci_intr_handle_t ih;
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const struct device_compatible_entry *dce;
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const char *chipname = NULL;
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const char *intrstr = NULL;
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bus_space_tag_t iot, memt;
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bus_space_handle_t ioh, memh;
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int ioh_valid, memh_valid;
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bus_addr_t addr;
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pcireg_t csr;
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int flags;
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int error;
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char intrbuf[PCI_INTRSTR_LEN];
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sc->sc_dev = self;
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/*
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* Map control/status registers.
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*/
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ioh_valid = (pci_mapreg_map(pa, FXP_PCI_IOBA, PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, NULL, NULL) == 0);
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/*
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* Version 2.1 of the PCI spec, page 196, "Address Maps":
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*
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* Prefetchable
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*
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* Set to one if there are no side effects on reads, the
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* device returns all bytes regardless of the byte enables,
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* and host bridges can merge processor writes into this
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* range without causing errors. Bit must be set to zero
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* otherwise.
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*
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* The 82557 incorrectly sets the "prefetchable" bit, resulting
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* in errors on systems which will do merged reads and writes.
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* These errors manifest themselves as all-bits-set when reading
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* from the EEPROM or other < 4 byte registers.
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*
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* We must work around this problem by always forcing the mapping
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* for memory space to be uncacheable. On systems which cannot
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* create an uncacheable mapping (because the firmware mapped it
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* into only cacheable/prefetchable space due to the "prefetchable"
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* bit), we can fall back onto i/o mapped access.
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*/
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memh_valid = 0;
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memt = pa->pa_memt;
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if (((pa->pa_flags & PCI_FLAGS_MEM_OKAY) != 0) &&
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pci_mapreg_info(pa->pa_pc, pa->pa_tag, FXP_PCI_MMBA,
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PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT,
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&addr, &sc->sc_size, &flags) == 0) {
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flags &= ~BUS_SPACE_MAP_PREFETCHABLE;
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if (bus_space_map(memt, addr, sc->sc_size, flags, &memh) == 0)
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memh_valid = 1;
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}
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if (memh_valid) {
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sc->sc_st = memt;
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sc->sc_sh = memh;
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/*
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* Enable address decoding for memory range in case BIOS or
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* UEFI didn't set it.
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*/
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csr = pci_conf_read(pa->pa_pc, pa->pa_tag,
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PCI_COMMAND_STATUS_REG);
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csr |= PCI_COMMAND_MEM_ENABLE;
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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csr);
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} else if (ioh_valid) {
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sc->sc_st = iot;
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sc->sc_sh = ioh;
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} else {
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aprint_error(": unable to map device registers\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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dce = pci_compatible_lookup(pa, compat_data);
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KASSERT(dce != NULL);
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sc->sc_rev = PCI_REVISION(pa->pa_class);
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switch (PCI_PRODUCT(dce->id)) {
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case PCI_PRODUCT_INTEL_8255X:
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case PCI_PRODUCT_INTEL_IN_BUSINESS:
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if (sc->sc_rev >= FXP_REV_82558_A4) {
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chipname = "i82558 Ethernet";
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sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB;
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/*
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* Enable the MWI command for memory writes.
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*/
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if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
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sc->sc_flags |= FXPF_MWI;
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}
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if (sc->sc_rev >= FXP_REV_82559_A0) {
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chipname = "i82559 Ethernet";
|
|
sc->sc_flags |= FXPF_82559_RXCSUM;
|
|
}
|
|
if (sc->sc_rev >= FXP_REV_82559S_A)
|
|
chipname = "i82559S Ethernet";
|
|
if (sc->sc_rev >= FXP_REV_82550) {
|
|
chipname = "i82550 Ethernet";
|
|
sc->sc_flags &= ~FXPF_82559_RXCSUM;
|
|
sc->sc_flags |= FXPF_EXT_RFA;
|
|
}
|
|
if (sc->sc_rev >= FXP_REV_82551_E)
|
|
chipname = "i82551 Ethernet";
|
|
|
|
/*
|
|
* Mark all i82559 and i82550 revisions as having
|
|
* the "resume bug". See i82557.c for details.
|
|
*/
|
|
if (sc->sc_rev >= FXP_REV_82559_A0)
|
|
sc->sc_flags |= FXPF_HAS_RESUME_BUG;
|
|
|
|
break;
|
|
|
|
case PCI_PRODUCT_INTEL_82559ER:
|
|
sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB;
|
|
|
|
/*
|
|
* i82559ER/82551ER don't support RX hardware checksumming
|
|
* even though it has a newer revision number than 82559_A0.
|
|
*/
|
|
|
|
/* All i82559 have the "resume bug". */
|
|
sc->sc_flags |= FXPF_HAS_RESUME_BUG;
|
|
|
|
/* Enable the MWI command for memory writes. */
|
|
if (pa->pa_flags & PCI_FLAGS_MWI_OKAY)
|
|
sc->sc_flags |= FXPF_MWI;
|
|
|
|
if (sc->sc_rev >= FXP_REV_82551_E)
|
|
chipname = "Intel i82551ER Ethernet";
|
|
|
|
break;
|
|
|
|
case PCI_PRODUCT_INTEL_82801BA_LAN:
|
|
case PCI_PRODUCT_INTEL_PRO_100_VE_0:
|
|
case PCI_PRODUCT_INTEL_PRO_100_VE_1:
|
|
case PCI_PRODUCT_INTEL_PRO_100_VM_0:
|
|
case PCI_PRODUCT_INTEL_PRO_100_VM_1:
|
|
case PCI_PRODUCT_INTEL_82562EH_HPNA_0:
|
|
case PCI_PRODUCT_INTEL_82562EH_HPNA_1:
|
|
case PCI_PRODUCT_INTEL_82562EH_HPNA_2:
|
|
case PCI_PRODUCT_INTEL_PRO_100_VM_2:
|
|
/*
|
|
* The ICH-2 and ICH-3 have the "resume bug".
|
|
*/
|
|
sc->sc_flags |= FXPF_HAS_RESUME_BUG;
|
|
/* FALLTHROUGH */
|
|
|
|
default:
|
|
if (sc->sc_rev >= FXP_REV_82558_A4)
|
|
sc->sc_flags |= FXPF_FC|FXPF_EXT_TXCB;
|
|
if (sc->sc_rev >= FXP_REV_82559_A0)
|
|
sc->sc_flags |= FXPF_82559_RXCSUM;
|
|
|
|
break;
|
|
}
|
|
|
|
pci_aprint_devinfo_fancy(pa, "Ethernet controller",
|
|
(chipname != NULL ? chipname : dce->data), 1);
|
|
|
|
/* Make sure bus-mastering is enabled. */
|
|
pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
|
|
pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
|
|
PCI_COMMAND_MASTER_ENABLE);
|
|
|
|
/*
|
|
* Under some circumstances (such as APM suspend/resume
|
|
* cycles, and across ACPI power state changes), the
|
|
* i82257-family can lose the contents of critical PCI
|
|
* configuration registers, causing the card to be
|
|
* non-responsive and useless. This occurs on the Sony VAIO
|
|
* Z505-series, among others. Preserve them here so they can
|
|
* be later restored (by fxp_pci_confreg_restore()).
|
|
*/
|
|
psc->psc_pc = pc;
|
|
psc->psc_tag = pa->pa_tag;
|
|
psc->psc_regs[PCI_COMMAND_STATUS_REG>>2] =
|
|
pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
|
|
psc->psc_regs[PCI_BHLC_REG>>2] =
|
|
pci_conf_read(pc, pa->pa_tag, PCI_BHLC_REG);
|
|
psc->psc_regs[(PCI_MAPREG_START+0x0)>>2] =
|
|
pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x0);
|
|
psc->psc_regs[(PCI_MAPREG_START+0x4)>>2] =
|
|
pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x4);
|
|
psc->psc_regs[(PCI_MAPREG_START+0x8)>>2] =
|
|
pci_conf_read(pc, pa->pa_tag, PCI_MAPREG_START+0x8);
|
|
|
|
/* power up chip */
|
|
switch ((error = pci_activate(pa->pa_pc, pa->pa_tag, self,
|
|
pci_activate_null))) {
|
|
case EOPNOTSUPP:
|
|
break;
|
|
case 0:
|
|
sc->sc_enable = fxp_pci_enable;
|
|
sc->sc_disable = NULL;
|
|
break;
|
|
default:
|
|
aprint_error_dev(self, "cannot activate %d\n", error);
|
|
return;
|
|
}
|
|
|
|
/* Restore PCI configuration registers. */
|
|
fxp_pci_confreg_restore(psc);
|
|
|
|
sc->sc_enabled = 1;
|
|
|
|
/*
|
|
* Map and establish our interrupt.
|
|
*/
|
|
if (pci_intr_map(pa, &ih)) {
|
|
aprint_error_dev(self, "couldn't map interrupt\n");
|
|
return;
|
|
}
|
|
intrstr = pci_intr_string(pc, ih, intrbuf, sizeof(intrbuf));
|
|
sc->sc_ih = pci_intr_establish_xname(pc, ih, IPL_NET, fxp_intr, sc,
|
|
device_xname(self));
|
|
if (sc->sc_ih == NULL) {
|
|
aprint_error_dev(self, "couldn't establish interrupt");
|
|
if (intrstr != NULL)
|
|
aprint_error(" at %s", intrstr);
|
|
aprint_error("\n");
|
|
return;
|
|
}
|
|
aprint_normal_dev(self, "interrupting at %s\n", intrstr);
|
|
|
|
/* Finish off the attach. */
|
|
fxp_attach(sc);
|
|
if (sc->sc_disable != NULL)
|
|
fxp_disable(sc);
|
|
|
|
/* Add a suspend hook to restore PCI config state */
|
|
if (pmf_device_register(self, NULL, fxp_pci_resume))
|
|
pmf_class_network_register(self, &sc->sc_ethercom.ec_if);
|
|
else
|
|
aprint_error_dev(self, "couldn't establish power handler\n");
|
|
}
|
|
|
|
static int
|
|
fxp_pci_enable(struct fxp_softc *sc)
|
|
{
|
|
struct fxp_pci_softc *psc = (void *) sc;
|
|
|
|
#if 0
|
|
printf("%s: going to power state D0\n", device_xname(self));
|
|
#endif
|
|
|
|
/* Now restore the configuration registers. */
|
|
fxp_pci_confreg_restore(psc);
|
|
|
|
return 0;
|
|
}
|