301 lines
11 KiB
C
301 lines
11 KiB
C
/* $NetBSD: ciss_pci.c,v 1.22 2020/07/14 17:23:58 jdolecek Exp $ */
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/* $OpenBSD: ciss_pci.c,v 1.9 2005/12/13 15:56:01 brad Exp $ */
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/*
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* Copyright (c) 2005 Michael Shalayeff
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* All rights reserved.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF MIND, USE, DATA OR PROFITS, WHETHER IN
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* AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
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* OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ciss_pci.c,v 1.22 2020/07/14 17:23:58 jdolecek Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/device.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <sys/bus.h>
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#include <dev/scsipi/scsipi_all.h>
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#include <dev/scsipi/scsipi_disk.h>
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#include <dev/scsipi/scsipiconf.h>
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#include <dev/ic/cissreg.h>
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#include <dev/ic/cissvar.h>
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#define CISS_BAR 0x10
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int ciss_pci_match(device_t, cfdata_t, void *);
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void ciss_pci_attach(device_t, device_t, void *);
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CFATTACH_DECL_NEW(ciss_pci, sizeof(struct ciss_softc),
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ciss_pci_match, ciss_pci_attach, NULL, NULL);
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static const struct {
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int vendor;
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int product;
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const char *name;
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} ciss_pci_devices[] = {
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#define CISS_PCI_DEVICE(v, p, d) { PCI_VENDOR_##v, PCI_PRODUCT_##v##_##p, d }
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CISS_PCI_DEVICE(COMPAQ, CSA532, "Compaq Smart Array 532"),
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CISS_PCI_DEVICE(COMPAQ, CSA5300, "Compaq Smart Array 5300 V1"),
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CISS_PCI_DEVICE(COMPAQ, CSA5300_2, "Compaq Smart Array 5300 V2"),
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CISS_PCI_DEVICE(COMPAQ, CSA5312, "Compaq Smart Array 5312"),
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CISS_PCI_DEVICE(COMPAQ, CSA5i, "Compaq Smart Array 5i"),
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CISS_PCI_DEVICE(COMPAQ, CSA5i_2, "Compaq Smart Array 5i V2"),
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CISS_PCI_DEVICE(COMPAQ, CSA6i, "Compaq Smart Array 6i"),
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CISS_PCI_DEVICE(COMPAQ, CSA641, "Compaq Smart Array 641"),
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CISS_PCI_DEVICE(COMPAQ, CSA642, "Compaq Smart Array 642"),
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CISS_PCI_DEVICE(COMPAQ, CSA6400, "Compaq Smart Array 6400"),
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CISS_PCI_DEVICE(COMPAQ, CSA6400EM, "Compaq Smart Array 6400EM"),
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CISS_PCI_DEVICE(COMPAQ, CSA6422, "Compaq Smart Array 6422"),
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CISS_PCI_DEVICE(COMPAQ, CSA64XX, "Compaq Smart Array 64XX"),
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CISS_PCI_DEVICE(HP, HPSAE200, "Smart Array E200"),
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CISS_PCI_DEVICE(HP, HPSAE200I_1, "HP Smart Array E200I-1"),
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CISS_PCI_DEVICE(HP, HPSAE200I_2, "HP Smart Array E200I-2"),
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CISS_PCI_DEVICE(HP, HPSAE200I_3, "HP Smart Array E200I-3"),
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CISS_PCI_DEVICE(HP, HPSAP600, "HP Smart Array P600"),
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CISS_PCI_DEVICE(HP, HPSAP800, "HP Smart Array P800"),
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CISS_PCI_DEVICE(HP, HPSAV100, "HP Smart Array V100"),
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CISS_PCI_DEVICE(HP, HPSA_1, "HP Smart Array 1"),
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CISS_PCI_DEVICE(HP, HPSA_2, "HP Smart Array 2"),
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CISS_PCI_DEVICE(HP, HPSA_3, "HP Smart Array 3"),
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CISS_PCI_DEVICE(HP, HPSA_4, "HP Smart Array 4"),
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CISS_PCI_DEVICE(HP, HPSA_5, "HP Smart Array 5"),
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CISS_PCI_DEVICE(HP, HPSA_6, "HP Smart Array 6"),
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CISS_PCI_DEVICE(HP, HPSA_7, "HP Smart Array 7"),
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CISS_PCI_DEVICE(HP, HPSA_8, "HP Smart Array 8"),
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CISS_PCI_DEVICE(HP, HPSA_9, "HP Smart Array 9"),
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CISS_PCI_DEVICE(HP, HPSA_10, "HP Smart Array 10"),
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CISS_PCI_DEVICE(HP, HPSA_11, "HP Smart Array 11"),
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CISS_PCI_DEVICE(HP, HPSA_12, "HP Smart Array 12"),
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CISS_PCI_DEVICE(HP, HPSA_13, "HP Smart Array 13"),
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CISS_PCI_DEVICE(HP, HPSA_P700M, "Smart Array P700m"),
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CISS_PCI_DEVICE(HP, HPSA_P212, "Smart Array P212"),
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CISS_PCI_DEVICE(HP, HPSA_P410, "Smart Array P410"),
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CISS_PCI_DEVICE(HP, HPSA_P410I, "Smart Array P410i"),
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CISS_PCI_DEVICE(HP, HPSA_P411, "Smart Array P411"),
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CISS_PCI_DEVICE(HP, HPSA_P812, "Smart Array P822"),
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CISS_PCI_DEVICE(HP, HPSA_P712M, "Smart Array P712m"),
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CISS_PCI_DEVICE(HP, HPSA_14, "Smart Array 14"),
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CISS_PCI_DEVICE(HP, HPSA_P222, "Smart Array P222"),
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CISS_PCI_DEVICE(HP, HPSA_P420, "Smart Array P420"),
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CISS_PCI_DEVICE(HP, HPSA_P421, "Smart Array P421"),
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CISS_PCI_DEVICE(HP, HPSA_P822, "Smart Array P822"),
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CISS_PCI_DEVICE(HP, HPSA_P420I, "Smart Array P420i"),
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CISS_PCI_DEVICE(HP, HPSA_P220I, "Smart Array P220i"),
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CISS_PCI_DEVICE(HP, HPSA_P721I, "Smart Array P721i"),
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CISS_PCI_DEVICE(HP, HPSA_P430I, "Smart Array P430i"),
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CISS_PCI_DEVICE(HP, HPSA_P830I, "Smart Array P830i"),
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CISS_PCI_DEVICE(HP, HPSA_P430, "Smart Array P430"),
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CISS_PCI_DEVICE(HP, HPSA_P431, "Smart Array P431"),
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CISS_PCI_DEVICE(HP, HPSA_P830, "Smart Array P830"),
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CISS_PCI_DEVICE(HP, HPSA_P731M, "Smart Array P731m"),
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CISS_PCI_DEVICE(HP, HPSA_P230I, "Smart Array P230i"),
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CISS_PCI_DEVICE(HP, HPSA_P530, "Smart Array P530"),
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CISS_PCI_DEVICE(HP, HPSA_P531, "Smart Array P531"),
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CISS_PCI_DEVICE(HP, HPSA_P244BR, "Smart Array P244br"),
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CISS_PCI_DEVICE(HP, HPSA_P741M, "Smart Array P741m"),
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CISS_PCI_DEVICE(HP, HPSA_H240AR, "Smart Array H240ar"),
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CISS_PCI_DEVICE(HP, HPSA_P440AR, "Smart Array H440ar"),
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CISS_PCI_DEVICE(HP, HPSA_P840AR, "Smart Array P840ar"),
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CISS_PCI_DEVICE(HP, HPSA_P440, "Smart Array P440"),
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CISS_PCI_DEVICE(HP, HPSA_P441, "Smart Array P441"),
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CISS_PCI_DEVICE(HP, HPSA_P841, "Smart Array P841"),
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CISS_PCI_DEVICE(HP, HPSA_H244BR, "Smart Array H244br"),
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CISS_PCI_DEVICE(HP, HPSA_H240, "Smart Array H240"),
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CISS_PCI_DEVICE(HP, HPSA_H241, "Smart Array H241"),
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CISS_PCI_DEVICE(HP, HPSA_P246BR, "Smart Array P246br"),
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CISS_PCI_DEVICE(HP, HPSA_P840, "Smart Array P840"),
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CISS_PCI_DEVICE(HP, HPSA_P542D, "Smart Array P542d"),
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CISS_PCI_DEVICE(HP, HPSA_P240NR, "Smart Array P240nr"),
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CISS_PCI_DEVICE(HP, HPSA_H240NR, "Smart Array H240nr"),
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};
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int
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ciss_pci_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa = aux;
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pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
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int i;
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for (i = 0; i < __arraycount(ciss_pci_devices); i++)
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{
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if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
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PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
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(PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
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PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
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return 1;
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}
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return 0;
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}
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void
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ciss_pci_attach(device_t parent, device_t self, void *aux)
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{
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struct ciss_softc *sc = device_private(self);
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struct pci_attach_args *pa = aux;
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bus_size_t size, cfgsz;
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pci_intr_handle_t *ih;
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const char *intrstr;
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int cfg_bar, memtype;
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pcireg_t reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
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int i;
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char intrbuf[PCI_INTRSTR_LEN];
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int (*intr_handler)(void *);
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sc->sc_dev = self;
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aprint_naive("\n");
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for (i = 0; i < __arraycount(ciss_pci_devices); i++)
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{
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if ((PCI_VENDOR(pa->pa_id) == ciss_pci_devices[i].vendor &&
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PCI_PRODUCT(pa->pa_id) == ciss_pci_devices[i].product) ||
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(PCI_VENDOR(reg) == ciss_pci_devices[i].vendor &&
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PCI_PRODUCT(reg) == ciss_pci_devices[i].product))
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{
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aprint_normal(": %s\n", ciss_pci_devices[i].name);
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break;
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}
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}
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memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, CISS_BAR);
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if (memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT) &&
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memtype != (PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT)) {
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aprint_error_dev(self, "wrong BAR type\n");
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return;
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}
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if (pci_mapreg_map(pa, CISS_BAR, memtype, 0,
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&sc->sc_iot, &sc->sc_ioh, NULL, &size)) {
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aprint_error_dev(self, "can't map controller i/o space\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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sc->iem = CISS_INTR_OPQ_SA5;
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reg = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
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if (PCI_VENDOR(reg) == PCI_VENDOR_COMPAQ &&
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(PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5i ||
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PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA532 ||
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PCI_PRODUCT(reg) == PCI_PRODUCT_COMPAQ_CSA5312))
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sc->iem = CISS_INTR_OPQ_SA5B;
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cfg_bar = bus_space_read_2(sc->sc_iot, sc->sc_ioh, CISS_CFG_BAR);
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sc->cfgoff = bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_CFG_OFF);
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if (cfg_bar != CISS_BAR) {
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if (pci_mapreg_map(pa, cfg_bar, PCI_MAPREG_TYPE_MEM, 0,
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NULL, &sc->cfg_ioh, NULL, &cfgsz)) {
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aprint_error_dev(self,
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"can't map controller config space\n");
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
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return;
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}
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} else {
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sc->cfg_ioh = sc->sc_ioh;
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cfgsz = size;
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}
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if (sc->cfgoff + sizeof(struct ciss_config) > cfgsz) {
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aprint_error_dev(self, "unfit config space\n");
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
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if (cfg_bar != CISS_BAR)
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bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
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return;
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}
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/* Read the configuration */
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bus_space_read_region_4(sc->sc_iot, sc->cfg_ioh, sc->cfgoff,
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(u_int32_t *)&sc->cfg, sizeof(sc->cfg) / 4);
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/* disable interrupts until ready */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) |
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sc->iem | CISS_INTR_OPQ | CISS_INTR_MSI);
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int counts[PCI_INTR_TYPE_SIZE] = {
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[PCI_INTR_TYPE_INTX] = 1,
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[PCI_INTR_TYPE_MSI] = 0,
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[PCI_INTR_TYPE_MSIX] = 0,
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};
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int max_type = PCI_INTR_TYPE_INTX;
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/*
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* Allow MSI/MSI-X only if PERFORMANT method is supported, SIMPLE
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* doesn't seem to work with MSI.
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*/
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if (CISS_PERF_SUPPORTED(sc)) {
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#if 1
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counts[PCI_INTR_TYPE_MSI] = counts[PCI_INTR_TYPE_MSIX] = 1;
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max_type = PCI_INTR_TYPE_MSIX;
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#endif
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sc->iem |= CISS_INTR_OPQ | CISS_INTR_MSI;
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}
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if (pci_intr_alloc(pa, &ih, counts, max_type)) {
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aprint_error_dev(self, "can't map interrupt\n");
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
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if (cfg_bar != CISS_BAR)
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bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih[0], intrbuf, sizeof(intrbuf));
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switch (pci_intr_type(pa->pa_pc, ih[0])) {
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case PCI_INTR_TYPE_INTX:
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intr_handler = CISS_PERF_SUPPORTED(sc)
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? ciss_intr_perf_intx : ciss_intr_simple_intx;
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break;
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default:
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KASSERT(CISS_PERF_SUPPORTED(sc));
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intr_handler = ciss_intr_perf_msi;
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break;
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}
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sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih[0], IPL_BIO,
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intr_handler, sc, device_xname(self));
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if (!sc->sc_ih) {
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aprint_error_dev(sc->sc_dev, "can't establish interrupt");
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if (intrstr)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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pci_intr_release(pa->pa_pc, ih, 1);
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
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if (cfg_bar != CISS_BAR)
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bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
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return;
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}
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aprint_normal_dev(self, "interrupting at %s\n", intrstr);
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aprint_normal("%s", device_xname(sc->sc_dev));
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if (ciss_attach(sc)) {
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pci_intr_disestablish(pa->pa_pc, sc->sc_ih);
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sc->sc_ih = NULL;
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bus_space_unmap(sc->sc_iot, sc->sc_ioh, size);
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if (cfg_bar != CISS_BAR)
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bus_space_unmap(sc->sc_iot, sc->cfg_ioh, cfgsz);
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return;
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}
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/* enable interrupts now */
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bus_space_write_4(sc->sc_iot, sc->sc_ioh, CISS_IMR,
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bus_space_read_4(sc->sc_iot, sc->sc_ioh, CISS_IMR) & ~sc->iem);
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}
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