992 lines
24 KiB
C
992 lines
24 KiB
C
/* $NetBSD: auacer.c,v 1.39 2020/02/29 06:34:30 isaki Exp $ */
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/*-
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* Copyright (c) 2004, 2008 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Lennart Augustsson.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Acer Labs M5455 audio driver
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*
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* Acer provides data sheets after signing an NDA, so this is guess work.
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* The chip behaves somewhat like the Intel i8x0, so this driver
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* is loosely based on the auich driver. Additional information taken from
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* the ALSA intel8x0.c driver (which handles M5455 as well).
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*
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* As an historical note one can observe that the auich driver borrows
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* lot from the first NetBSD PCI audio driver, the eap driver. But this
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* is not attributed anywhere.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: auacer.c,v 1.39 2020/02/29 06:34:30 isaki Exp $");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/kmem.h>
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#include <sys/device.h>
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#include <sys/fcntl.h>
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#include <sys/proc.h>
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#include <dev/pci/pcidevs.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/auacerreg.h>
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#include <sys/audioio.h>
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#include <dev/audio/audio_if.h>
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#include <sys/bus.h>
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#include <dev/ic/ac97reg.h>
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#include <dev/ic/ac97var.h>
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struct auacer_dma {
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bus_dmamap_t map;
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void *addr;
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bus_dma_segment_t segs[1];
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int nsegs;
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size_t size;
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struct auacer_dma *next;
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};
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#define DMAADDR(p) ((p)->map->dm_segs[0].ds_addr)
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#define KERNADDR(p) ((void *)((p)->addr))
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struct auacer_cdata {
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struct auacer_dmalist ic_dmalist_pcmo[ALI_DMALIST_MAX];
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};
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struct auacer_chan {
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uint32_t ptr;
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uint32_t start, p, end;
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uint32_t blksize, fifoe;
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uint32_t ack;
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uint32_t port;
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struct auacer_dmalist *dmalist;
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void (*intr)(void *);
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void *arg;
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};
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struct auacer_softc {
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device_t sc_dev;
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void *sc_ih;
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kmutex_t sc_lock;
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kmutex_t sc_intr_lock;
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audio_device_t sc_audev;
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bus_space_tag_t iot;
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bus_space_handle_t mix_ioh;
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bus_space_handle_t aud_ioh;
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bus_dma_tag_t dmat;
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struct ac97_codec_if *codec_if;
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struct ac97_host_if host_if;
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/* DMA scatter-gather lists. */
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bus_dmamap_t sc_cddmamap;
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#define sc_cddma sc_cddmamap->dm_segs[0].ds_addr
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struct auacer_cdata *sc_cdata;
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struct auacer_chan sc_pcmo;
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struct auacer_dma *sc_dmas;
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pci_chipset_tag_t sc_pc;
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pcitag_t sc_pt;
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int sc_dmamap_flags;
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#define AUACER_NFORMATS 3
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struct audio_format sc_formats[AUACER_NFORMATS];
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};
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#define READ1(sc, a) bus_space_read_1(sc->iot, sc->aud_ioh, a)
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#define READ2(sc, a) bus_space_read_2(sc->iot, sc->aud_ioh, a)
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#define READ4(sc, a) bus_space_read_4(sc->iot, sc->aud_ioh, a)
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#define WRITE1(sc, a, v) bus_space_write_1(sc->iot, sc->aud_ioh, a, v)
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#define WRITE2(sc, a, v) bus_space_write_2(sc->iot, sc->aud_ioh, a, v)
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#define WRITE4(sc, a, v) bus_space_write_4(sc->iot, sc->aud_ioh, a, v)
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/* Debug */
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#ifdef AUACER_DEBUG
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#define DPRINTF(l,x) do { if (auacer_debug & (l)) printf x; } while(0)
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int auacer_debug = 0;
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#define ALI_DEBUG_CODECIO 0x0001
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#define ALI_DEBUG_DMA 0x0002
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#define ALI_DEBUG_INTR 0x0004
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#define ALI_DEBUG_API 0x0008
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#define ALI_DEBUG_MIXERAPI 0x0010
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#else
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#define DPRINTF(x,y) /* nothing */
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#endif
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static int auacer_intr(void *);
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static int auacer_query_format(void *, audio_format_query_t *);
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static int auacer_set_format(void *, int,
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const audio_params_t *, const audio_params_t *,
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audio_filter_reg_t *, audio_filter_reg_t *);
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static int auacer_halt_output(void *);
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static int auacer_halt_input(void *);
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static int auacer_getdev(void *, struct audio_device *);
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static int auacer_set_port(void *, mixer_ctrl_t *);
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static int auacer_get_port(void *, mixer_ctrl_t *);
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static int auacer_query_devinfo(void *, mixer_devinfo_t *);
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static void *auacer_allocm(void *, int, size_t);
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static void auacer_freem(void *, void *, size_t);
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static size_t auacer_round_buffersize(void *, int, size_t);
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static int auacer_get_props(void *);
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static int auacer_trigger_output(void *, void *, void *, int,
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void (*)(void *), void *,
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const audio_params_t *);
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static int auacer_trigger_input(void *, void *, void *, int,
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void (*)(void *), void *,
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const audio_params_t *);
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static int auacer_alloc_cdata(struct auacer_softc *);
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static int auacer_allocmem(struct auacer_softc *, size_t, size_t,
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struct auacer_dma *);
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static int auacer_freemem(struct auacer_softc *, struct auacer_dma *);
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static void auacer_get_locks(void *, kmutex_t **, kmutex_t **);
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static bool auacer_resume(device_t, const pmf_qual_t *);
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static int auacer_set_rate(struct auacer_softc *, int, u_int);
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static void auacer_reset(struct auacer_softc *sc);
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static const struct audio_hw_if auacer_hw_if = {
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.query_format = auacer_query_format,
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.set_format = auacer_set_format,
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.halt_output = auacer_halt_output,
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.halt_input = auacer_halt_input,
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.getdev = auacer_getdev,
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.set_port = auacer_set_port,
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.get_port = auacer_get_port,
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.query_devinfo = auacer_query_devinfo,
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.allocm = auacer_allocm,
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.freem = auacer_freem,
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.round_buffersize = auacer_round_buffersize,
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.get_props = auacer_get_props,
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.trigger_output = auacer_trigger_output,
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.trigger_input = auacer_trigger_input,
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.get_locks = auacer_get_locks,
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};
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#define AUACER_FORMATS_4CH 1
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#define AUACER_FORMATS_6CH 2
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#define AUACER_FORMAT(aumode, ch, chmask) \
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{ \
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.mode = (aumode), \
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.encoding = AUDIO_ENCODING_SLINEAR_LE, \
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.validbits = 16, \
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.precision = 16, \
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.channels = (ch), \
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.channel_mask = (chmask), \
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.frequency_type = 9, \
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.frequency = { 8000, 11025, 12000, 16000, 22050, \
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24000, 32000, 44100, 48000, }, \
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}
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static const struct audio_format auacer_formats[AUACER_NFORMATS] = {
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AUACER_FORMAT(AUMODE_PLAY | AUMODE_RECORD, 2, AUFMT_STEREO),
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AUACER_FORMAT(AUMODE_PLAY , 4, AUFMT_SURROUND4),
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AUACER_FORMAT(AUMODE_PLAY , 6, AUFMT_DOLBY_5_1),
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};
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static int auacer_attach_codec(void *, struct ac97_codec_if *);
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static int auacer_read_codec(void *, uint8_t, uint16_t *);
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static int auacer_write_codec(void *, uint8_t, uint16_t);
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static int auacer_reset_codec(void *);
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static int
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auacer_match(device_t parent, cfdata_t match, void *aux)
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{
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struct pci_attach_args *pa;
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pa = (struct pci_attach_args *)aux;
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if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_ALI &&
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PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_ALI_M5455)
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return 1;
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return 0;
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}
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static void
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auacer_attach(device_t parent, device_t self, void *aux)
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{
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struct auacer_softc *sc;
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struct pci_attach_args *pa;
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pci_intr_handle_t ih;
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bus_size_t aud_size;
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pcireg_t v;
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const char *intrstr;
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int i;
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char intrbuf[PCI_INTRSTR_LEN];
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sc = device_private(self);
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sc->sc_dev = self;
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pa = aux;
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aprint_normal(": Acer Labs M5455 Audio controller\n");
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if (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, &sc->iot,
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&sc->aud_ioh, NULL, &aud_size)) {
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aprint_error(": can't map i/o space\n");
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return;
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}
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sc->sc_pc = pa->pa_pc;
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sc->sc_pt = pa->pa_tag;
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sc->dmat = pa->pa_dmat;
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sc->sc_dmamap_flags = BUS_DMA_COHERENT; /* XXX remove */
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mutex_init(&sc->sc_lock, MUTEX_DEFAULT, IPL_NONE);
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mutex_init(&sc->sc_intr_lock, MUTEX_DEFAULT, IPL_AUDIO);
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/* enable bus mastering */
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v = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
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pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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v | PCI_COMMAND_MASTER_ENABLE);
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/* Map and establish the interrupt. */
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if (pci_intr_map(pa, &ih)) {
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aprint_error_dev(sc->sc_dev, "can't map interrupt\n");
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mutex_destroy(&sc->sc_lock);
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mutex_destroy(&sc->sc_intr_lock);
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return;
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}
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intrstr = pci_intr_string(pa->pa_pc, ih, intrbuf, sizeof(intrbuf));
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sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, ih, IPL_AUDIO,
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auacer_intr, sc, device_xname(self));
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if (sc->sc_ih == NULL) {
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aprint_error_dev(sc->sc_dev, "can't establish interrupt");
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if (intrstr != NULL)
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aprint_error(" at %s", intrstr);
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aprint_error("\n");
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mutex_destroy(&sc->sc_lock);
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mutex_destroy(&sc->sc_intr_lock);
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return;
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}
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aprint_normal_dev(sc->sc_dev, "interrupting at %s\n", intrstr);
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strlcpy(sc->sc_audev.name, "M5455 AC97", MAX_AUDIO_DEV_LEN);
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snprintf(sc->sc_audev.version, MAX_AUDIO_DEV_LEN,
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"0x%02x", PCI_REVISION(pa->pa_class));
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strlcpy(sc->sc_audev.config, device_xname(sc->sc_dev), MAX_AUDIO_DEV_LEN);
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/* Set up DMA lists. */
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auacer_alloc_cdata(sc);
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sc->sc_pcmo.dmalist = sc->sc_cdata->ic_dmalist_pcmo;
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sc->sc_pcmo.ptr = 0;
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sc->sc_pcmo.port = ALI_BASE_PO;
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DPRINTF(ALI_DEBUG_DMA, ("auacer_attach: lists %p\n",
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sc->sc_pcmo.dmalist));
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sc->host_if.arg = sc;
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sc->host_if.attach = auacer_attach_codec;
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sc->host_if.read = auacer_read_codec;
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sc->host_if.write = auacer_write_codec;
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sc->host_if.reset = auacer_reset_codec;
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if (ac97_attach(&sc->host_if, self, &sc->sc_lock) != 0) {
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mutex_destroy(&sc->sc_lock);
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mutex_destroy(&sc->sc_intr_lock);
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return;
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}
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/* setup audio_format */
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memcpy(sc->sc_formats, auacer_formats, sizeof(auacer_formats));
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mutex_enter(&sc->sc_lock);
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if (!AC97_IS_4CH(sc->codec_if))
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AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_4CH]);
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if (!AC97_IS_6CH(sc->codec_if))
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AUFMT_INVALIDATE(&sc->sc_formats[AUACER_FORMATS_6CH]);
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if (AC97_IS_FIXED_RATE(sc->codec_if)) {
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for (i = 0; i < AUACER_NFORMATS; i++) {
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sc->sc_formats[i].frequency_type = 1;
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sc->sc_formats[i].frequency[0] = 48000;
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}
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}
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mutex_spin_enter(&sc->sc_intr_lock);
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auacer_reset(sc);
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mutex_spin_exit(&sc->sc_intr_lock);
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mutex_exit(&sc->sc_lock);
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audio_attach_mi(&auacer_hw_if, sc, sc->sc_dev);
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if (!pmf_device_register(self, NULL, auacer_resume))
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aprint_error_dev(self, "couldn't establish power handler\n");
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}
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CFATTACH_DECL_NEW(auacer, sizeof(struct auacer_softc),
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auacer_match, auacer_attach, NULL, NULL);
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static int
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auacer_ready_codec(struct auacer_softc *sc, int mask)
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{
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int count;
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for (count = 0; count < 0x7f; count++) {
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int val = READ1(sc, ALI_CSPSR);
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if (val & mask)
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return 0;
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}
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aprint_normal("auacer_ready_codec: AC97 codec ready timeout.\n");
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return EBUSY;
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}
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static int
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auacer_sema_codec(struct auacer_softc *sc)
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{
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int ttime;
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ttime = 100;
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while (ttime-- && (READ4(sc, ALI_CAS) & ALI_CAS_SEM_BUSY))
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delay(1);
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if (!ttime)
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aprint_normal("auacer_sema_codec: timeout\n");
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return auacer_ready_codec(sc, ALI_CSPSR_CODEC_READY);
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}
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static int
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auacer_read_codec(void *v, uint8_t reg, uint16_t *val)
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{
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struct auacer_softc *sc;
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sc = v;
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if (auacer_sema_codec(sc))
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return EIO;
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reg |= ALI_CPR_ADDR_READ;
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#if 0
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if (ac97->num)
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reg |= ALI_CPR_ADDR_SECONDARY;
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#endif
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WRITE2(sc, ALI_CPR_ADDR, reg);
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if (auacer_ready_codec(sc, ALI_CSPSR_READ_OK))
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return EIO;
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*val = READ2(sc, ALI_SPR);
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DPRINTF(ALI_DEBUG_CODECIO, ("auacer_read_codec: reg=0x%x val=0x%x\n",
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reg, *val));
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return 0;
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}
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int
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auacer_write_codec(void *v, uint8_t reg, uint16_t val)
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{
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struct auacer_softc *sc;
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DPRINTF(ALI_DEBUG_CODECIO, ("auacer_write_codec: reg=0x%x val=0x%x\n",
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reg, val));
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sc = v;
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if (auacer_sema_codec(sc))
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return EIO;
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WRITE2(sc, ALI_CPR, val);
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#if 0
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if (ac97->num)
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reg |= ALI_CPR_ADDR_SECONDARY;
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#endif
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WRITE2(sc, ALI_CPR_ADDR, reg);
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auacer_ready_codec(sc, ALI_CSPSR_WRITE_OK);
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return 0;
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}
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static int
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auacer_attach_codec(void *v, struct ac97_codec_if *cif)
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{
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struct auacer_softc *sc;
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sc = v;
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sc->codec_if = cif;
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return 0;
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}
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static int
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auacer_reset_codec(void *v)
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{
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struct auacer_softc *sc;
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uint32_t reg;
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int i;
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sc = v;
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i = 0;
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reg = READ4(sc, ALI_SCR);
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if ((reg & 2) == 0) /* Cold required */
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reg |= 2;
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else
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reg |= 1; /* Warm */
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reg &= ~0x80000000; /* ACLink on */
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WRITE4(sc, ALI_SCR, reg);
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while (i < 10) {
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if ((READ4(sc, ALI_INTERRUPTSR) & ALI_INT_GPIO) == 0)
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break;
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delay(50000); /* XXX */
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i++;
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}
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if (i == 10) {
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return EIO;
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}
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for (i = 0; i < 10; i++) {
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reg = READ4(sc, ALI_RTSR);
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if (reg & 0x80) /* primary codec */
|
|
break;
|
|
WRITE4(sc, ALI_RTSR, reg | 0x80);
|
|
delay(50000); /* XXX */
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
auacer_reset(struct auacer_softc *sc)
|
|
{
|
|
WRITE4(sc, ALI_SCR, ALI_SCR_RESET);
|
|
WRITE4(sc, ALI_FIFOCR1, 0x83838383);
|
|
WRITE4(sc, ALI_FIFOCR2, 0x83838383);
|
|
WRITE4(sc, ALI_FIFOCR3, 0x83838383);
|
|
WRITE4(sc, ALI_INTERFACECR, ALI_IF_PO); /* XXX pcm out only */
|
|
WRITE4(sc, ALI_INTERRUPTCR, 0x00000000);
|
|
WRITE4(sc, ALI_INTERRUPTSR, 0x00000000);
|
|
}
|
|
|
|
static int
|
|
auacer_query_format(void *v, audio_format_query_t *afp)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_API, ("%s\n", __func__));
|
|
sc = v;
|
|
return audio_query_format(sc->sc_formats, AUACER_NFORMATS, afp);
|
|
}
|
|
|
|
static int
|
|
auacer_set_rate(struct auacer_softc *sc, int mode, u_int srate)
|
|
{
|
|
int ret;
|
|
u_int ratetmp;
|
|
|
|
DPRINTF(ALI_DEBUG_API, ("auacer_set_rate: srate=%u\n", srate));
|
|
|
|
ratetmp = srate;
|
|
if (mode == AUMODE_RECORD)
|
|
return sc->codec_if->vtbl->set_rate(sc->codec_if,
|
|
AC97_REG_PCM_LR_ADC_RATE, &ratetmp);
|
|
ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
|
|
AC97_REG_PCM_FRONT_DAC_RATE, &ratetmp);
|
|
if (ret)
|
|
return ret;
|
|
ratetmp = srate;
|
|
ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
|
|
AC97_REG_PCM_SURR_DAC_RATE, &ratetmp);
|
|
if (ret)
|
|
return ret;
|
|
ratetmp = srate;
|
|
ret = sc->codec_if->vtbl->set_rate(sc->codec_if,
|
|
AC97_REG_PCM_LFE_DAC_RATE, &ratetmp);
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
auacer_set_format(void *v, int setmode,
|
|
const audio_params_t *play, const audio_params_t *rec,
|
|
audio_filter_reg_t *pfil, audio_filter_reg_t *rfil)
|
|
{
|
|
struct auacer_softc *sc;
|
|
const audio_params_t *p;
|
|
uint32_t control;
|
|
int mode, index;
|
|
|
|
DPRINTF(ALI_DEBUG_API, ("%s\n", __func__));
|
|
sc = v;
|
|
for (mode = AUMODE_RECORD; mode != -1;
|
|
mode = mode == AUMODE_RECORD ? AUMODE_PLAY : -1) {
|
|
if ((setmode & mode) == 0)
|
|
continue;
|
|
|
|
p = mode == AUMODE_PLAY ? play : rec;
|
|
|
|
index = audio_indexof_format(sc->sc_formats, AUACER_NFORMATS,
|
|
mode, p);
|
|
/* p points HW encoding */
|
|
if (sc->sc_formats[index].frequency_type != 1
|
|
&& auacer_set_rate(sc, mode, p->sample_rate))
|
|
return EINVAL;
|
|
if (mode == AUMODE_PLAY) {
|
|
control = READ4(sc, ALI_SCR);
|
|
control &= ~ALI_SCR_PCM_246_MASK;
|
|
if (p->channels == 4)
|
|
control |= ALI_SCR_PCM_4;
|
|
else if (p->channels == 6)
|
|
control |= ALI_SCR_PCM_6;
|
|
WRITE4(sc, ALI_SCR, control);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
auacer_halt(struct auacer_softc *sc, struct auacer_chan *chan)
|
|
{
|
|
uint32_t val;
|
|
uint8_t port;
|
|
uint32_t slot;
|
|
|
|
port = chan->port;
|
|
DPRINTF(ALI_DEBUG_API, ("auacer_halt: port=0x%x\n", port));
|
|
chan->intr = 0;
|
|
|
|
slot = ALI_PORT2SLOT(port);
|
|
|
|
val = READ4(sc, ALI_DMACR);
|
|
val |= 1 << (slot+16); /* pause */
|
|
val &= ~(1 << slot); /* no start */
|
|
WRITE4(sc, ALI_DMACR, val);
|
|
WRITE1(sc, port + ALI_OFF_CR, 0);
|
|
while (READ1(sc, port + ALI_OFF_CR))
|
|
;
|
|
/* reset whole DMA things */
|
|
WRITE1(sc, port + ALI_OFF_CR, ALI_CR_RR);
|
|
/* clear interrupts */
|
|
WRITE1(sc, port + ALI_OFF_SR, READ1(sc, port+ALI_OFF_SR) | ALI_SR_W1TC);
|
|
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(port));
|
|
}
|
|
|
|
static int
|
|
auacer_halt_output(void *v)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_output\n"));
|
|
sc = v;
|
|
auacer_halt(sc, &sc->sc_pcmo);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
auacer_halt_input(void *v)
|
|
{
|
|
DPRINTF(ALI_DEBUG_DMA, ("auacer_halt_input\n"));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
auacer_getdev(void *v, struct audio_device *adp)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_API, ("auacer_getdev\n"));
|
|
sc = v;
|
|
*adp = sc->sc_audev;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
auacer_set_port(void *v, mixer_ctrl_t *cp)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_set_port\n"));
|
|
sc = v;
|
|
return sc->codec_if->vtbl->mixer_set_port(sc->codec_if, cp);
|
|
}
|
|
|
|
static int
|
|
auacer_get_port(void *v, mixer_ctrl_t *cp)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_get_port\n"));
|
|
sc = v;
|
|
return sc->codec_if->vtbl->mixer_get_port(sc->codec_if, cp);
|
|
}
|
|
|
|
static int
|
|
auacer_query_devinfo(void *v, mixer_devinfo_t *dp)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
DPRINTF(ALI_DEBUG_MIXERAPI, ("auacer_query_devinfo\n"));
|
|
sc = v;
|
|
return sc->codec_if->vtbl->query_devinfo(sc->codec_if, dp);
|
|
}
|
|
|
|
static void *
|
|
auacer_allocm(void *v, int direction, size_t size)
|
|
{
|
|
struct auacer_softc *sc;
|
|
struct auacer_dma *p;
|
|
int error;
|
|
|
|
if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
|
|
return NULL;
|
|
|
|
p = kmem_zalloc(sizeof(*p), KM_SLEEP);
|
|
sc = v;
|
|
error = auacer_allocmem(sc, size, 0, p);
|
|
if (error) {
|
|
kmem_free(p, sizeof(*p));
|
|
return NULL;
|
|
}
|
|
|
|
p->next = sc->sc_dmas;
|
|
sc->sc_dmas = p;
|
|
|
|
return KERNADDR(p);
|
|
}
|
|
|
|
static void
|
|
auacer_freem(void *v, void *ptr, size_t size)
|
|
{
|
|
struct auacer_softc *sc;
|
|
struct auacer_dma *p, **pp;
|
|
|
|
sc = v;
|
|
for (pp = &sc->sc_dmas; (p = *pp) != NULL; pp = &p->next) {
|
|
if (KERNADDR(p) == ptr) {
|
|
auacer_freemem(sc, p);
|
|
*pp = p->next;
|
|
kmem_free(p, sizeof(*p));
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
static size_t
|
|
auacer_round_buffersize(void *v, int direction, size_t size)
|
|
{
|
|
|
|
if (size > (ALI_DMALIST_MAX * ALI_DMASEG_MAX))
|
|
size = ALI_DMALIST_MAX * ALI_DMASEG_MAX;
|
|
|
|
return size;
|
|
}
|
|
|
|
static int
|
|
auacer_get_props(void *v)
|
|
{
|
|
|
|
return AUDIO_PROP_PLAYBACK | AUDIO_PROP_CAPTURE |
|
|
AUDIO_PROP_INDEPENDENT | AUDIO_PROP_FULLDUPLEX;
|
|
}
|
|
|
|
static void
|
|
auacer_get_locks(void *v, kmutex_t **intr, kmutex_t **proc)
|
|
{
|
|
struct auacer_softc *sc;
|
|
|
|
sc = v;
|
|
*intr = &sc->sc_intr_lock;
|
|
*proc = &sc->sc_lock;
|
|
}
|
|
|
|
static void
|
|
auacer_add_entry(struct auacer_chan *chan)
|
|
{
|
|
struct auacer_dmalist *q;
|
|
|
|
q = &chan->dmalist[chan->ptr];
|
|
|
|
DPRINTF(ALI_DEBUG_INTR,
|
|
("auacer_add_entry: %p = %x @ 0x%x\n",
|
|
q, chan->blksize / 2, chan->p));
|
|
|
|
q->base = htole32(chan->p);
|
|
q->len = htole32((chan->blksize / ALI_SAMPLE_SIZE) | ALI_DMAF_IOC);
|
|
chan->p += chan->blksize;
|
|
if (chan->p >= chan->end)
|
|
chan->p = chan->start;
|
|
|
|
if (++chan->ptr >= ALI_DMALIST_MAX)
|
|
chan->ptr = 0;
|
|
}
|
|
|
|
static void
|
|
auacer_upd_chan(struct auacer_softc *sc, struct auacer_chan *chan)
|
|
{
|
|
uint32_t sts;
|
|
uint32_t civ;
|
|
|
|
sts = READ2(sc, chan->port + ALI_OFF_SR);
|
|
/* intr ack */
|
|
WRITE2(sc, chan->port + ALI_OFF_SR, sts & ALI_SR_W1TC);
|
|
WRITE4(sc, ALI_INTERRUPTSR, ALI_PORT2INTR(chan->port));
|
|
|
|
DPRINTF(ALI_DEBUG_INTR, ("auacer_upd_chan: sts=0x%x\n", sts));
|
|
|
|
if (sts & ALI_SR_DMA_INT_FIFO) {
|
|
printf("%s: fifo underrun # %u\n",
|
|
device_xname(sc->sc_dev), ++chan->fifoe);
|
|
}
|
|
|
|
civ = READ1(sc, chan->port + ALI_OFF_CIV);
|
|
|
|
DPRINTF(ALI_DEBUG_INTR,("auacer_intr: civ=%u ptr=%u\n",civ,chan->ptr));
|
|
|
|
/* XXX */
|
|
while (chan->ptr != civ) {
|
|
auacer_add_entry(chan);
|
|
}
|
|
|
|
WRITE1(sc, chan->port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
|
|
|
|
while (chan->ack != civ) {
|
|
if (chan->intr) {
|
|
DPRINTF(ALI_DEBUG_INTR,("auacer_upd_chan: callback\n"));
|
|
chan->intr(chan->arg);
|
|
}
|
|
chan->ack++;
|
|
if (chan->ack >= ALI_DMALIST_MAX)
|
|
chan->ack = 0;
|
|
}
|
|
}
|
|
|
|
static int
|
|
auacer_intr(void *v)
|
|
{
|
|
struct auacer_softc *sc;
|
|
int ret, intrs;
|
|
|
|
sc = v;
|
|
|
|
DPRINTF(ALI_DEBUG_INTR, ("auacer_intr: intrs=0x%x\n",
|
|
READ4(sc, ALI_INTERRUPTSR)));
|
|
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
|
intrs = READ4(sc, ALI_INTERRUPTSR);
|
|
ret = 0;
|
|
if (intrs & ALI_INT_PCMOUT) {
|
|
auacer_upd_chan(sc, &sc->sc_pcmo);
|
|
ret++;
|
|
}
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
|
|
|
return ret != 0;
|
|
}
|
|
|
|
static void
|
|
auacer_setup_chan(struct auacer_softc *sc, struct auacer_chan *chan,
|
|
uint32_t start, uint32_t size, uint32_t blksize,
|
|
void (*intr)(void *), void *arg)
|
|
{
|
|
uint32_t port, slot;
|
|
uint32_t offs, val;
|
|
|
|
chan->start = start;
|
|
chan->ptr = 0;
|
|
chan->p = chan->start;
|
|
chan->end = chan->start + size;
|
|
chan->blksize = blksize;
|
|
chan->ack = 0;
|
|
chan->intr = intr;
|
|
chan->arg = arg;
|
|
|
|
auacer_add_entry(chan);
|
|
auacer_add_entry(chan);
|
|
|
|
port = chan->port;
|
|
slot = ALI_PORT2SLOT(port);
|
|
|
|
WRITE1(sc, port + ALI_OFF_CIV, 0);
|
|
WRITE1(sc, port + ALI_OFF_LVI, (chan->ptr - 1) & ALI_LVI_MASK);
|
|
offs = (char *)chan->dmalist - (char *)sc->sc_cdata;
|
|
WRITE4(sc, port + ALI_OFF_BDBAR, sc->sc_cddma + offs);
|
|
WRITE1(sc, port + ALI_OFF_CR,
|
|
ALI_CR_IOCE | ALI_CR_FEIE | ALI_CR_LVBIE | ALI_CR_RPBM);
|
|
val = READ4(sc, ALI_DMACR);
|
|
val &= ~(1 << (slot+16)); /* no pause */
|
|
val |= 1 << slot; /* start */
|
|
WRITE4(sc, ALI_DMACR, val);
|
|
}
|
|
|
|
static int
|
|
auacer_trigger_output(void *v, void *start, void *end, int blksize,
|
|
void (*intr)(void *), void *arg, const audio_params_t *param)
|
|
{
|
|
struct auacer_softc *sc;
|
|
struct auacer_dma *p;
|
|
uint32_t size;
|
|
|
|
DPRINTF(ALI_DEBUG_DMA,
|
|
("auacer_trigger_output(%p, %p, %d, %p, %p, %p)\n",
|
|
start, end, blksize, intr, arg, param));
|
|
sc = v;
|
|
for (p = sc->sc_dmas; p && KERNADDR(p) != start; p = p->next)
|
|
continue;
|
|
if (!p) {
|
|
printf("auacer_trigger_output: bad addr %p\n", start);
|
|
return (EINVAL);
|
|
}
|
|
|
|
size = (char *)end - (char *)start;
|
|
auacer_setup_chan(sc, &sc->sc_pcmo, DMAADDR(p), size, blksize,
|
|
intr, arg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
auacer_trigger_input(void *v, void *start, void *end,
|
|
int blksize, void (*intr)(void *), void *arg,
|
|
const audio_params_t *param)
|
|
{
|
|
return EINVAL;
|
|
}
|
|
|
|
static int
|
|
auacer_allocmem(struct auacer_softc *sc, size_t size, size_t align,
|
|
struct auacer_dma *p)
|
|
{
|
|
int error;
|
|
|
|
p->size = size;
|
|
error = bus_dmamem_alloc(sc->dmat, p->size, align, 0,
|
|
p->segs, sizeof(p->segs)/sizeof(p->segs[0]),
|
|
&p->nsegs, BUS_DMA_WAITOK);
|
|
if (error)
|
|
return error;
|
|
|
|
error = bus_dmamem_map(sc->dmat, p->segs, p->nsegs, p->size,
|
|
&p->addr, BUS_DMA_WAITOK|sc->sc_dmamap_flags);
|
|
if (error)
|
|
goto free;
|
|
|
|
error = bus_dmamap_create(sc->dmat, p->size, 1, p->size,
|
|
0, BUS_DMA_WAITOK, &p->map);
|
|
if (error)
|
|
goto unmap;
|
|
|
|
error = bus_dmamap_load(sc->dmat, p->map, p->addr, p->size, NULL,
|
|
BUS_DMA_WAITOK);
|
|
if (error)
|
|
goto destroy;
|
|
return (0);
|
|
|
|
destroy:
|
|
bus_dmamap_destroy(sc->dmat, p->map);
|
|
unmap:
|
|
bus_dmamem_unmap(sc->dmat, p->addr, p->size);
|
|
free:
|
|
bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
|
|
return error;
|
|
}
|
|
|
|
static int
|
|
auacer_freemem(struct auacer_softc *sc, struct auacer_dma *p)
|
|
{
|
|
|
|
bus_dmamap_unload(sc->dmat, p->map);
|
|
bus_dmamap_destroy(sc->dmat, p->map);
|
|
bus_dmamem_unmap(sc->dmat, p->addr, p->size);
|
|
bus_dmamem_free(sc->dmat, p->segs, p->nsegs);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
auacer_alloc_cdata(struct auacer_softc *sc)
|
|
{
|
|
bus_dma_segment_t seg;
|
|
int error, rseg;
|
|
|
|
/*
|
|
* Allocate the control data structure, and create and load the
|
|
* DMA map for it.
|
|
*/
|
|
if ((error = bus_dmamem_alloc(sc->dmat,
|
|
sizeof(struct auacer_cdata),
|
|
PAGE_SIZE, 0, &seg, 1, &rseg, 0)) != 0) {
|
|
aprint_error_dev(sc->sc_dev, "unable to allocate control data, error = %d\n",
|
|
error);
|
|
goto fail_0;
|
|
}
|
|
|
|
if ((error = bus_dmamem_map(sc->dmat, &seg, rseg,
|
|
sizeof(struct auacer_cdata),
|
|
(void **) &sc->sc_cdata,
|
|
sc->sc_dmamap_flags)) != 0) {
|
|
aprint_error_dev(sc->sc_dev, "unable to map control data, error = %d\n",
|
|
error);
|
|
goto fail_1;
|
|
}
|
|
|
|
if ((error = bus_dmamap_create(sc->dmat, sizeof(struct auacer_cdata), 1,
|
|
sizeof(struct auacer_cdata), 0, 0,
|
|
&sc->sc_cddmamap)) != 0) {
|
|
aprint_error_dev(sc->sc_dev, "unable to create control data DMA map, "
|
|
"error = %d\n", error);
|
|
goto fail_2;
|
|
}
|
|
|
|
if ((error = bus_dmamap_load(sc->dmat, sc->sc_cddmamap,
|
|
sc->sc_cdata, sizeof(struct auacer_cdata),
|
|
NULL, 0)) != 0) {
|
|
aprint_error_dev(sc->sc_dev, "unable to load control data DMA map, "
|
|
"error = %d\n", error);
|
|
goto fail_3;
|
|
}
|
|
|
|
return 0;
|
|
|
|
fail_3:
|
|
bus_dmamap_destroy(sc->dmat, sc->sc_cddmamap);
|
|
fail_2:
|
|
bus_dmamem_unmap(sc->dmat, (void *) sc->sc_cdata,
|
|
sizeof(struct auacer_cdata));
|
|
fail_1:
|
|
bus_dmamem_free(sc->dmat, &seg, rseg);
|
|
fail_0:
|
|
return error;
|
|
}
|
|
|
|
static bool
|
|
auacer_resume(device_t dv, const pmf_qual_t *qual)
|
|
{
|
|
struct auacer_softc *sc = device_private(dv);
|
|
|
|
mutex_enter(&sc->sc_lock);
|
|
mutex_spin_enter(&sc->sc_intr_lock);
|
|
auacer_reset_codec(sc);
|
|
mutex_spin_exit(&sc->sc_intr_lock);
|
|
delay(1000);
|
|
sc->codec_if->vtbl->restore_ports(sc->codec_if);
|
|
mutex_exit(&sc->sc_lock);
|
|
|
|
return true;
|
|
}
|