117 lines
3.3 KiB
C
117 lines
3.3 KiB
C
/* $NetBSD: pl061.c,v 1.3 2021/04/24 23:36:55 thorpej Exp $ */
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/*
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* Copyright (c) 2018 Jonathan A. Kollasch
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: pl061.c,v 1.3 2021/04/24 23:36:55 thorpej Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/intr.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/kmem.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiovar.h>
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#include "gpio.h"
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#include <dev/ic/pl061reg.h>
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#include <dev/ic/pl061var.h>
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void
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plgpio_attach(struct plgpio_softc *sc)
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{
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struct gpiobus_attach_args gba;
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u_int pin;
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sc->sc_gc.gp_cookie = sc;
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sc->sc_gc.gp_pin_read = plgpio_pin_read;
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sc->sc_gc.gp_pin_write = plgpio_pin_write;
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sc->sc_gc.gp_pin_ctl = plgpio_pin_ctl;
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const uint32_t cnf = PLGPIO_READ(sc, PL061_GPIOAFSEL_REG) |
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sc->sc_reserved_mask;
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for (pin = 0; pin < 8; pin++) {
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sc->sc_pins[pin].pin_num = pin;
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/* skip pins in hardware control mode */
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if ((cnf & __BIT(pin)) != 0)
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continue;
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sc->sc_pins[pin].pin_caps =
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GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
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GPIO_PIN_TRISTATE;
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sc->sc_pins[pin].pin_state =
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plgpio_pin_read(sc, pin);
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}
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memset(&gba, 0, sizeof(gba));
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gba.gba_gc = &sc->sc_gc;
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gba.gba_pins = sc->sc_pins;
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gba.gba_npins = 8;
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#if NGPIO > 0
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config_found(sc->sc_dev, &gba, gpiobus_print, CFARG_EOL);
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#endif
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}
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int
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plgpio_pin_read(void *priv, int pin)
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{
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struct plgpio_softc * const sc = priv;
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const uint32_t v = PLGPIO_READ(sc, PL061_GPIODATA_REG(1<<pin));
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return (v >> pin) & 1;
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}
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void
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plgpio_pin_write(void *priv, int pin, int val)
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{
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struct plgpio_softc * const sc = priv;
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PLGPIO_WRITE(sc, PL061_GPIODATA_REG(1 << pin), val << pin);
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}
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void
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plgpio_pin_ctl(void *priv, int pin, int flags)
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{
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struct plgpio_softc * const sc = priv;
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uint32_t v;
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if (flags & GPIO_PIN_INPUT) {
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v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
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v &= ~(1 << pin);
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PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
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} else if (flags & GPIO_PIN_OUTPUT) {
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v = PLGPIO_READ(sc, PL061_GPIODIR_REG);
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v |= (1 << pin);
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PLGPIO_WRITE(sc, PL061_GPIODIR_REG, v);
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}
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}
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