68 lines
2.7 KiB
C
68 lines
2.7 KiB
C
/* $NetBSD: ns16550reg.h,v 1.13 2019/01/11 23:10:41 thorpej Exp $ */
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/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)ns16550.h 7.1 (Berkeley) 5/9/91
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*/
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/*
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* NS16550 UART registers
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*/
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#define com_data 0 /* data register (R/W) */
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#define com_dlbl 0 /* divisor latch low (W) */
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#define com_dlbh 1 /* divisor latch high (W) */
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#define com_ier 1 /* interrupt enable (W) */
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#define com_iir 2 /* interrupt identification (R) */
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#define com_fifo 2 /* FIFO control (W) */
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#define com_lctl 3 /* line control register (R/W) */
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#define com_cfcr 3 /* line control register (R/W) */
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#define com_lcr com_cfcr
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#define com_mcr 4 /* modem control register (R/W) */
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#define com_lsr 5 /* line status register (R/W) */
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#define com_msr 6 /* modem status register (R/W) */
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#define com_scratch 7 /* scratch register (R/W) */
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/*
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* Additional registers present on TI OMAP hardware
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*/
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#define com_mdr1 8 /* mode definition register 1 (OMAP) */
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/*
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* Additional register present in NS16750
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*/
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#define com_usr 31 /* status register (R) (16750/SUNXI) */
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/*
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* Additional registers present on Allwinner hardware
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*/
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#define com_tfl 32 /* transmit fifo level (R) (SUNXI) */
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#define com_rfl 33 /* receive fifo level (R) (SUNXI) */
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#define com_halt 41 /* halt tx (R/W) (SUNXI) */
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