2652188cc4
interface controllers (of varying intelligence levels). Contributed by Wasabi Systems, Inc. Primarily written by Steve Woodford, with some modification by me.
179 lines
4.6 KiB
C
179 lines
4.6 KiB
C
/* $NetBSD: i2c_bitbang.c,v 1.1 2003/09/30 00:35:31 thorpej Exp $ */
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/*
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* Copyright (c) 2003 Wasabi Systems, Inc.
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* All rights reserved.
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*
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* Written by Jason R. Thorpe for Wasabi Systems, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed for the NetBSD Project by
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* Wasabi Systems, Inc.
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* 4. The name of Wasabi Systems, Inc. may not be used to endorse
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* or promote products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Common module for bit-bang'ing an I2C bus.
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*/
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#include <sys/param.h>
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#include <dev/i2c/i2cvar.h>
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#include <dev/i2c/i2c_bitbang.h>
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#define SET(x) ops->ibo_set_bits(v, (x))
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#define DIR(x) ops->ibo_set_dir(v, (x))
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#define READ ops->ibo_read_bits(v)
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#define SDA ops->ibo_bits[I2C_BIT_SDA] /* i2c signal */
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#define SCL ops->ibo_bits[I2C_BIT_SCL] /* i2c signal */
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#define OUTPUT ops->ibo_bits[I2C_BIT_OUTPUT] /* SDA is output */
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#define INPUT ops->ibo_bits[I2C_BIT_INPUT] /* SDA is input */
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/*ARGSUSED*/
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int
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i2c_bitbang_send_start(void *v, int flags, i2c_bitbang_ops_t ops)
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{
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DIR(OUTPUT);
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SET(SDA | SCL);
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delay(5); /* bus free time (4.7 uS) */
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SET( SCL);
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delay(4); /* start hold time (4.0 uS) */
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SET( 0);
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delay(5); /* clock low time (4.7 uS) */
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return (0);
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}
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/*ARGSUSED*/
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int
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i2c_bitbang_send_stop(void *v, int flags, i2c_bitbang_ops_t ops)
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{
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DIR(OUTPUT);
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SET( SCL);
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delay(4); /* stop setup time (4.0 uS) */
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SET(SDA | SCL);
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return (0);
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}
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int
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i2c_bitbang_initiate_xfer(void *v, i2c_addr_t addr, int flags,
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i2c_bitbang_ops_t ops)
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{
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int i2caddr;
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/* XXX Only support 7-bit addressing for now. */
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if ((addr & 0x78) == 0x78)
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return (EINVAL);
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i2caddr = (addr << 1) | ((flags & I2C_F_READ) ? 1 : 0);
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(void) i2c_bitbang_send_start(v, flags, ops);
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return (i2c_bitbang_write_byte(v, i2caddr, flags & ~I2C_F_STOP, ops));
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}
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int
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i2c_bitbang_read_byte(void *v, uint8_t *valp, int flags,
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i2c_bitbang_ops_t ops)
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{
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int i;
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uint8_t val = 0;
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uint32_t bit;
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DIR(INPUT);
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SET(SDA );
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for (i = 0; i < 8; i++) {
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val <<= 1;
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SET(SDA | SCL);
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delay(4); /* clock high time (4.0 uS) */
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if (READ & SDA)
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val |= 1;
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SET(SDA );
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delay(5); /* clock low time (4.7 uS) */
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}
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bit = (flags & I2C_F_LAST) ? SDA : 0;
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DIR(OUTPUT);
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SET(bit );
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delay(1); /* data setup time (250 nS) */
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SET(bit | SCL);
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delay(4); /* clock high time (4.0 uS) */
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SET(bit );
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delay(5); /* clock low time (4.7 uS) */
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DIR(INPUT);
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SET(SDA );
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delay(5);
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if ((flags & (I2C_F_STOP | I2C_F_LAST)) == (I2C_F_STOP | I2C_F_LAST))
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(void) i2c_bitbang_send_stop(v, flags, ops);
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*valp = val;
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return (0);
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}
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int
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i2c_bitbang_write_byte(void *v, uint8_t val, int flags,
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i2c_bitbang_ops_t ops)
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{
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uint32_t bit;
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uint8_t mask;
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int error;
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DIR(OUTPUT);
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for (mask = 0x80; mask != 0; mask >>= 1) {
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bit = (val & mask) ? SDA : 0;
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SET(bit );
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delay(1); /* data setup time (250 nS) */
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SET(bit | SCL);
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delay(4); /* clock high time (4.0 uS) */
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SET(bit );
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delay(5); /* clock low time (4.7 uS) */
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}
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DIR(INPUT);
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SET(SDA );
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delay(5);
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SET(SDA | SCL);
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delay(4);
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error = (READ & SDA) ? EIO : 0;
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SET(SDA );
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delay(5);
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if (flags & I2C_F_STOP)
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(void) i2c_bitbang_send_stop(v, flags, ops);
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return (error);
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}
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