298 lines
9.8 KiB
C
298 lines
9.8 KiB
C
/* $NetBSD: atppcreg.h,v 1.6 2016/09/15 21:45:37 jdolecek Exp $ */
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/*-
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* Copyright (c) 2001 Alcove - Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* FreeBSD: src/sys/isa/ppcreg.h,v 1.10.2.4 2001/10/02 05:21:45 nsouch Exp
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*
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*/
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#ifndef __ATPPCREG_H
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#define __ATPPCREG_H
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/* Generic register definitions as offsets from a base address */
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#define ATPPC_SPP_DTR 0 /* SPP data register */
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#define ATPPC_ECP_A_FIFO 0 /* ECP Address fifo register */
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#define ATPPC_SPP_STR 1 /* SPP status register */
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#define ATPPC_SPP_CTR 2 /* SPP control register */
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#define ATPPC_EPP_ADDR 3 /* EPP address register (8 bit) */
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#define ATPPC_EPP_DATA 4 /* EPP data register (8, 16, 32 bit) */
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#define ATPPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
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#define ATPPC_ECP_CNFGA 0x400 /* Configuration register A */
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#define ATPPC_ECP_CNFGB 0x401 /* Configuration register B */
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#define ATPPC_ECP_ECR 0x402 /* ECP extended control register */
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/* ECP control register commands/modes */
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#define ATPPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
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#define ATPPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
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#define ATPPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
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#define ATPPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
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#define ATPPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
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/* ecr register - bits 5 through 7 */
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#define ATPPC_ECR_STD 0x00 /* Standard mode */
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#define ATPPC_ECR_PS2 0x20 /* Bidirectional mode */
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#define ATPPC_ECR_FIFO 0x40 /* Fast Centronics mode */
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#define ATPPC_ECR_ECP 0x60 /* ECP mode */
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#define ATPPC_ECR_EPP 0x80 /* EPP mode */
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#define ATPPC_ECR_TST 0xd0 /* Test mode*/
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#define ATPPC_ECR_CFG 0xe0 /* Test mode*/
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/* To set "inverted" flags, do AND. Otherwise, do OR */
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/* 0 & x = 0, 1 | x = 1 */
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/* Clear flags: n(var) is equivalent to var = 0.
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#define n(flags) (~(flags) & (flags))*/
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/* Invert flags
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#define inv(flags) (~(flags))*/
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/* SPP mode control register bit positions. */
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#define STROBE 0x01
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#define AUTOFEED 0x02
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#define nINIT 0x04
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#define SELECTIN 0x08
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#define IRQENABLE 0x10
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#define PCD 0x20
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/*
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#define nSTROBE inv(STROBE)
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#define nAUTOFEED inv(AUTOFEED)
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#define INIT inv(nINIT)
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#define nSELECTIN inv(SELECTIN)
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#define nPCD inv(PCD)
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*/
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/* SPP status register bit positions. */
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#define TIMEOUT 0x01
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#define nFAULT 0x08
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#define SELECT 0x10
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#define PERROR 0x20
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#define nACK 0x40
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#define nBUSY 0x80
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/* Flags indicating ready condition */
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#define SPP_READY (SELECT | nFAULT | nBUSY)
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#define SPP_MASK (SELECT | nFAULT | PERROR | nBUSY)
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/* Byte mode signals */
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#define HOSTCLK STROBE /* Also ECP mode signal */
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#define HOSTBUSY AUTOFEED
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#define ACTIVE1284 SELECTIN /* Also ECP mode signal */
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#define PTRCLK nACK
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#define PTRBUSY nBUSY
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#define ACKDATAREQ PERROR
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#define XFLAG SELECT /* Also ECP mode signal */
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#define nDATAVAIL nFAULT
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/* ECP mode signals */
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#define HOSTACK AUTOFEED
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#define nREVREQ nINIT
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#define PERICLK nACK
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#define PERIACK nBUSY
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#define nACKREV PERROR
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#define nPERIREQ nFAULT
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/* EPP mode signals */
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#define nWRITE STROBE
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#define nDATASTB AUTOFEED
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#define nADDRSTB SELECTIN
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#define nWAIT nBUSY
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#define nRESET nINIT
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#define nINTR nACK
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/*
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* Useful macros for reading/writing registers.
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*/
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/* Reading macros */
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#define atppc_r_dtr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \
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ATPPC_SPP_DTR)
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#define atppc_r_str(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \
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ATPPC_SPP_STR)
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#define atppc_r_ctr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \
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ATPPC_SPP_CTR)
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#define atppc_r_eppA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\
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ATPPC_EPP_ADDR)
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#define atppc_r_eppD(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\
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ATPPC_EPP_DATA)
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#define atppc_r_eppD_multi(atppc, buf, count) bus_space_read_multi_1( \
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(atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count))
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#define atppc_r_cnfgA(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\
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ATPPC_ECP_CNFGA)
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#define atppc_r_cnfgB(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh,\
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ATPPC_ECP_CNFGB)
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#define atppc_r_ecr(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \
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ATPPC_ECP_ECR)
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#define atppc_r_fifo(atppc) bus_space_read_1((atppc)->sc_iot, (atppc)->sc_ioh, \
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ATPPC_ECP_D_FIFO)
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#define atppc_r_fifo_multi(atppc, buf, count) bus_space_read_multi_1( \
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(atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count))
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/* Writing macros */
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#define atppc_w_dtr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_SPP_DTR, (byte))
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#define atppc_w_str(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_SPP_STR, (byte))
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#define atppc_w_ctr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_SPP_CTR, (byte))
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#define atppc_w_eppA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_EPP_ADDR, (byte))
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#define atppc_w_eppD(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_EPP_DATA, (byte))
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#define atppc_w_eppD_multi(atppc, buf, count) bus_space_write_multi_1( \
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(atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_EPP_DATA, (buf), (count))
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#define atppc_w_cnfgA(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_ECP_CNFGA, (byte))
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#define atppc_w_cnfgB(atppc, byte) bus_space_read_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_ECP_CNFGB, (byte))
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#define atppc_w_ecr(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_ECP_ECR, (byte))
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#define atppc_w_fifo(atppc, byte) bus_space_write_1((atppc)->sc_iot, \
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(atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (byte))
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#define atppc_w_fifo_multi(atppc, buf, count) bus_space_write_multi_1( \
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(atppc)->sc_iot, (atppc)->sc_ioh, ATPPC_ECP_D_FIFO, (buf), (count))
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/* Barrier macros for reads/writes */
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#define atppc_barrier_r(atppc) bus_space_barrier((atppc)->sc_iot, \
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(atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_READ)
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#define atppc_barrier_w(atppc) bus_space_barrier((atppc)->sc_iot, \
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(atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE)
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#define atppc_barrier(atppc) bus_space_barrier((atppc)->sc_iot, \
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(atppc)->sc_ioh, 0, IO_LPTSIZE, BUS_SPACE_BARRIER_WRITE | \
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BUS_SPACE_BARRIER_READ)
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/*
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* Register defines for the PC873xx parts
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*/
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#define PC873_FER 0x00
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#define PC873_PPENABLE (1<<0)
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#define PC873_FAR 0x01
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#define PC873_PTR 0x02
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#define PC873_CFGLOCK (1<<6)
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#define PC873_EPPRDIR (1<<7)
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#define PC873_EXTENDED (1<<7)
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#define PC873_LPTBIRQ7 (1<<3)
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#define PC873_FCR 0x03
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#define PC873_ZWS (1<<5)
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#define PC873_ZWSPWDN (1<<6)
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#define PC873_PCR 0x04
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#define PC873_EPPEN (1<<0)
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#define PC873_EPP19 (1<<1)
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#define PC873_ECPEN (1<<2)
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#define PC873_ECPCLK (1<<3)
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#define PC873_PMC 0x06
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#define PC873_TUP 0x07
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#define PC873_SID 0x08
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#define PC873_PNP0 0x1b
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#define PC873_PNP1 0x1c
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#define PC873_LPTBA 0x19
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/*
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* Register defines for the SMC FDC37C66xGT parts
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*/
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/* Init codes */
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#define SMC665_iCODE 0x55
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#define SMC666_iCODE 0x44
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/* Base configuration ports */
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#define SMC66x_CSR 0x3F0
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#define SMC666_CSR 0x370 /* hard-configured value for 666 */
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/* Bits */
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#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
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#define SMC_CR1_MODE (1<<3) /* bit 3 */
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#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
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#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
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/* Extended modes */
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#define SMC_SPP 0x0 /* SPP */
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#define SMC_EPPSPP 0x1 /* EPP and SPP */
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#define SMC_ECP 0x2 /* ECP */
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#define SMC_ECPEPP 0x3 /* ECP and EPP */
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/*
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* Register defines for the SMC FDC37C935 parts
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*/
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/* Configuration ports */
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#define SMC935_CFG 0x370
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#define SMC935_IND 0x370
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#define SMC935_DAT 0x371
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/* Registers */
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#define SMC935_LOGDEV 0x7
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#define SMC935_ID 0x20
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#define SMC935_PORTHI 0x60
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#define SMC935_PORTLO 0x61
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#define SMC935_PPMODE 0xf0
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/* Parallel port modes */
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#define SMC935_SPP 0x38 + 0
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#define SMC935_EPP19SPP 0x38 + 1
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#define SMC935_ECP 0x38 + 2
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#define SMC935_ECPEPP19 0x38 + 3
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#define SMC935_CENT 0x38 + 4
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#define SMC935_EPP17SPP 0x38 + 5
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#define SMC935_UNUSED 0x38 + 6
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#define SMC935_ECPEPP17 0x38 + 7
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/*
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* Register defines for the Winbond W83877F parts
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*/
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#define WINB_W83877F_ID 0xa
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#define WINB_W83877AF_ID 0xb
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/* Configuration bits */
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#define WINB_HEFERE (1<<5) /* CROC bit 5 */
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#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
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#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
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#define WINB_CHIPID 0xf /* CR9 bits 0-3 */
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#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
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#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
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#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
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/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
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#define WINB_W83757 0x0
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#define WINB_EXTFDC 0x4
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#define WINB_EXTADP 0x8
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#define WINB_EXT2FDD 0xc
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#define WINB_JOYSTICK 0x80
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#define WINB_PARALLEL 0x80
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#define WINB_EPP_SPP 0x4
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#define WINB_ECP 0x8
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#define WINB_ECP_EPP 0xc
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#endif /* __ATPPCREG_H */
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