26ab868e68
caveats, but works quite well in a lot of MP cases, and all UP cases that I have tested. Parts of this will hopefully be reworked in the not-too-distant future.
282 lines
6.0 KiB
C
282 lines
6.0 KiB
C
/* $NetBSD: cpufunc.h,v 1.22 2002/10/01 12:57:04 fvdl Exp $ */
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Charles M. Hannum.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _I386_CPUFUNC_H_
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#define _I386_CPUFUNC_H_
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/*
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* Functions to provide access to i386-specific instructions.
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*/
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <machine/specialreg.h>
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#ifdef _KERNEL
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static __inline void
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invlpg(u_int addr)
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{
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__asm __volatile("invlpg (%0)" : : "r" (addr) : "memory");
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}
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static __inline void
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lidt(void *p)
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{
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__asm __volatile("lidt (%0)" : : "r" (p));
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}
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static __inline void
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lldt(u_short sel)
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{
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__asm __volatile("lldt %0" : : "r" (sel));
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}
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static __inline void
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ltr(u_short sel)
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{
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__asm __volatile("ltr %0" : : "r" (sel));
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}
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static __inline void
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lcr0(u_int val)
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{
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__asm __volatile("movl %0,%%cr0" : : "r" (val));
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}
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static __inline u_int
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rcr0(void)
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{
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u_int val;
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__asm __volatile("movl %%cr0,%0" : "=r" (val));
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return val;
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}
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static __inline u_int
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rcr2(void)
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{
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u_int val;
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__asm __volatile("movl %%cr2,%0" : "=r" (val));
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return val;
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}
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static __inline void
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lcr3(u_int val)
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{
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__asm __volatile("movl %0,%%cr3" : : "r" (val));
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}
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static __inline u_int
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rcr3(void)
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{
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u_int val;
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__asm __volatile("movl %%cr3,%0" : "=r" (val));
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return val;
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}
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static __inline void
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lcr4(u_int val)
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{
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__asm __volatile("movl %0,%%cr4" : : "r" (val));
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}
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static __inline u_int
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rcr4(void)
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{
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u_int val;
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__asm __volatile("movl %%cr4,%0" : "=r" (val));
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return val;
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}
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static __inline void
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tlbflush(void)
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{
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u_int val;
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val = rcr3();
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lcr3(val);
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}
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static __inline void
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tlbflushg(void)
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{
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/*
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* Big hammer: flush all TLB entries, including ones from PTE's
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* with the G bit set. This should only be necessary if TLB
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* shootdown falls far behind.
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*
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* Intel Architecture Software Developer's Manual, Volume 3,
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* System Programming, section 9.10, "Invalidating the
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* Translation Lookaside Buffers (TLBS)":
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* "The following operations invalidate all TLB entries, irrespective
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* of the setting of the G flag:
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* ...
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* "(P6 family processors only): Writing to control register CR4 to
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* modify the PSE, PGE, or PAE flag."
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*
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* (the alternatives not quoted above are not an option here.)
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*
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* If PGE is not in use, we reload CR3 for the benefit of
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* pre-P6-family processors.
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*/
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#if defined(I686_CPU)
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if (cpu_feature & CPUID_PGE) {
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u_int cr4 = rcr4();
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lcr4(cr4 & ~CR4_PGE);
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lcr4(cr4);
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} else
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#endif
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tlbflush();
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}
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#ifdef notyet
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void setidt __P((int idx, /*XXX*/caddr_t func, int typ, int dpl));
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#endif
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/* debug register */
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void dr0(caddr_t, u_int32_t, u_int32_t, u_int32_t);
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static __inline u_int
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rdr6(void)
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{
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u_int val;
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__asm __volatile("movl %%dr6,%0" : "=r" (val));
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return val;
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}
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static __inline void
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ldr6(u_int val)
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{
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__asm __volatile("movl %0,%%dr6" : : "r" (val));
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}
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/* XXXX ought to be in psl.h with spl() functions */
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static __inline void
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disable_intr(void)
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{
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__asm __volatile("cli");
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}
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static __inline void
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enable_intr(void)
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{
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__asm __volatile("sti");
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}
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static __inline u_long
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read_eflags(void)
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{
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u_long ef;
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__asm __volatile("pushfl; popl %0" : "=r" (ef));
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return (ef);
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}
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static __inline void
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write_eflags(u_long ef)
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{
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__asm __volatile("pushl %0; popfl" : : "r" (ef));
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}
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static __inline u_int64_t
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rdmsr(u_int msr)
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{
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u_int64_t rv;
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__asm __volatile("rdmsr" : "=A" (rv) : "c" (msr));
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return (rv);
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}
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static __inline void
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wrmsr(u_int msr, u_int64_t newval)
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{
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__asm __volatile("wrmsr" : : "A" (newval), "c" (msr));
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}
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static __inline void
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wbinvd(void)
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{
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__asm __volatile("wbinvd");
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}
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static __inline u_int64_t
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rdtsc(void)
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{
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u_int64_t rv;
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__asm __volatile("rdtsc" : "=A" (rv));
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return (rv);
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}
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static __inline u_int64_t
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rdpmc(u_int pmc)
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{
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u_int64_t rv;
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__asm __volatile("rdpmc" : "=A" (rv) : "c" (pmc));
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return (rv);
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}
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/* Break into DDB/KGDB. */
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static __inline void
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breakpoint(void)
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{
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__asm __volatile("int $3");
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}
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/*
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* XXX Maybe these don't belong here...
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*/
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extern int (*copyout_func)(const void *, void *, size_t);
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extern int (*copyin_func)(const void *, void *, size_t);
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int i386_copyout(const void *, void *, size_t);
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int i486_copyout(const void *, void *, size_t);
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int i386_copyin(const void *, void *, size_t);
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#endif /* _KERNEL */
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#endif /* !_I386_CPUFUNC_H_ */
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