395 lines
12 KiB
C
395 lines
12 KiB
C
/* $NetBSD: espvar.h,v 1.2 1996/11/02 06:52:24 briggs Exp $ */
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/*
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* Copyright (c) 1994 Peter Galbavy. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Peter Galbavy.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <machine/param.h>
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#if defined(__sparc__) && !defined(SPARC_DRIVER)
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#define SPARC_DRIVER
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#else
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#if (_MACHINE == mac68k) && !defined(MAC68K_DRIVER)
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#define MAC68K_DRIVER
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#endif
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#endif
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#define ESP_DEBUG 0
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#define ESP_ABORT_TIMEOUT 2000 /* time to wait for abort */
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#define FREQTOCCF(freq) (((freq + 4) / 5))
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/* esp revisions */
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#define ESP100 0x01
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#define ESP100A 0x02
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#define ESP200 0x03
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#define NCR53C94 0x04
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#define NCR53C96 0x05
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/*
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* ECB. Holds additional information for each SCSI command Comments: We
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* need a separate scsi command block because we may need to overwrite it
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* with a request sense command. Basicly, we refrain from fiddling with
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* the scsi_xfer struct (except do the expected updating of return values).
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* We'll generally update: xs->{flags,resid,error,sense,status} and
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* occasionally xs->retries.
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*/
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struct esp_ecb {
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TAILQ_ENTRY(esp_ecb) chain;
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struct scsi_xfer *xs; /* SCSI xfer ctrl block from above */
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int flags;
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#define ECB_ALLOC 0x01
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#define ECB_NEXUS 0x02
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#define ECB_SENSE 0x04
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#define ECB_ABORT 0x40
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#define ECB_RESET 0x80
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int timeout;
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struct scsi_generic cmd; /* SCSI command block */
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int clen;
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char *daddr; /* Saved data pointer */
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int dleft; /* Residue */
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u_char stat; /* SCSI status byte */
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#if ESP_DEBUG > 0
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char trace[1000];
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#endif
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};
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#if ESP_DEBUG > 0
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#define ECB_TRACE(ecb, msg, a, b) do { \
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const char *f = "[" msg "]"; \
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int n = strlen((ecb)->trace); \
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if (n < (sizeof((ecb)->trace)-100)) \
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sprintf((ecb)->trace + n, f, a, b); \
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} while(0)
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#else
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#define ECB_TRACE(ecb, msg, a, b)
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#endif
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/*
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* Some info about each (possible) target on the SCSI bus. This should
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* probably have been a "per target+lunit" structure, but we'll leave it at
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* this for now. Is there a way to reliably hook it up to sc->fordriver??
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*/
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struct esp_tinfo {
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int cmds; /* #commands processed */
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int dconns; /* #disconnects */
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int touts; /* #timeouts */
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int perrs; /* #parity errors */
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int senses; /* #request sense commands sent */
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ushort lubusy; /* What local units/subr. are busy? */
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u_char flags;
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#define T_NEED_TO_RESET 0x01 /* Should send a BUS_DEV_RESET */
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#define T_NEGOTIATE 0x02 /* (Re)Negotiate synchronous options */
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#define T_BUSY 0x04 /* Target is busy, i.e. cmd in progress */
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#define T_SYNCMODE 0x08 /* sync mode has been negotiated */
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#define T_SYNCHOFF 0x10 /* .. */
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#define T_RSELECTOFF 0x20 /* .. */
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u_char period; /* Period suggestion */
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u_char offset; /* Offset suggestion */
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} tinfo_t;
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/* Register a linenumber (for debugging) */
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#define LOGLINE(p)
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#define ESP_SHOWECBS 0x01
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#define ESP_SHOWINTS 0x02
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#define ESP_SHOWCMDS 0x04
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#define ESP_SHOWMISC 0x08
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#define ESP_SHOWTRAC 0x10
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#define ESP_SHOWSTART 0x20
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#define ESP_SHOWPHASE 0x40
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#define ESP_SHOWDMA 0x80
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#define ESP_SHOWCCMDS 0x100
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#define ESP_SHOWMSGS 0x200
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#ifdef ESP_DEBUG
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extern int esp_debug;
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#define ESP_ECBS(str) do {if (esp_debug & ESP_SHOWECBS) printf str;} while (0)
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#define ESP_MISC(str) do {if (esp_debug & ESP_SHOWMISC) printf str;} while (0)
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#define ESP_INTS(str) do {if (esp_debug & ESP_SHOWINTS) printf str;} while (0)
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#define ESP_TRACE(str) do {if (esp_debug & ESP_SHOWTRAC) printf str;} while (0)
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#define ESP_CMDS(str) do {if (esp_debug & ESP_SHOWCMDS) printf str;} while (0)
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#define ESP_START(str) do {if (esp_debug & ESP_SHOWSTART) printf str;}while (0)
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#define ESP_PHASE(str) do {if (esp_debug & ESP_SHOWPHASE) printf str;}while (0)
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#define ESP_DMA(str) do {if (esp_debug & ESP_SHOWDMA) printf str;}while (0)
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#define ESP_MSGS(str) do {if (esp_debug & ESP_SHOWMSGS) printf str;}while (0)
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#else
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#define ESP_ECBS(str)
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#define ESP_MISC(str)
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#define ESP_INTS(str)
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#define ESP_TRACE(str)
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#define ESP_CMDS(str)
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#define ESP_START(str)
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#define ESP_PHASE(str)
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#define ESP_DMA(str)
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#define ESP_MSGS(str)
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#endif
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#define ESP_MAX_MSG_LEN 8
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struct esp_softc {
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struct device sc_dev; /* us as a device */
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#ifdef SPARC_DRIVER
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struct sbusdev sc_sd; /* sbus device */
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struct intrhand sc_ih; /* intr handler */
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#endif
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struct evcnt sc_intrcnt; /* intr count */
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struct scsi_link sc_link; /* scsi lint struct */
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#ifdef SPARC_DRIVER
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volatile u_char *sc_reg; /* the registers */
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struct dma_softc *sc_dma; /* pointer to my dma */
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#else
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#ifdef MAC68K_DRIVER
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volatile u_char *sc_reg; /* the registers */
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struct dma_softc _sc_dma; /* my (fake) DMA structure */
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struct dma_softc *sc_dma; /* pointer to my (fake) DMA */
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u_char irq_mask; /* mask for clearing IRQ */
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#else
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volatile u_int32_t *sc_reg; /* the registers */
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struct tcds_slotconfig *sc_dma; /* DMA/slot info lives here. */
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void *sc_cookie; /* intr. handling cookie */
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#endif
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#endif
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/* register defaults */
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u_char sc_cfg1; /* Config 1 */
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u_char sc_cfg2; /* Config 2, not ESP100 */
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u_char sc_cfg3; /* Config 3, only ESP200 */
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u_char sc_ccf; /* Clock Conversion */
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u_char sc_timeout;
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/* register copies, see espreadregs() */
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u_char sc_espintr;
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u_char sc_espstat;
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u_char sc_espstep;
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u_char sc_espfflags;
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/* Lists of command blocks */
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TAILQ_HEAD(ecb_list, esp_ecb) free_list,
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ready_list,
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nexus_list;
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struct esp_ecb *sc_nexus; /* current command */
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struct esp_ecb sc_ecb[8]; /* one per target */
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struct esp_tinfo sc_tinfo[8];
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/* Data about the current nexus (updated for every cmd switch) */
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caddr_t sc_dp; /* Current data pointer */
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ssize_t sc_dleft; /* Data left to transfer */
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/* Adapter state */
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int sc_phase; /* Copy of what bus phase we are in */
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int sc_prevphase; /* Copy of what bus phase we were in */
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u_char sc_state; /* State applicable to the adapter */
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u_char sc_flags;
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u_char sc_selid;
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u_char sc_lastcmd;
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/* Message stuff */
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u_char sc_msgpriq; /* One or more messages to send (encoded) */
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u_char sc_msgout; /* What message is on its way out? */
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u_char sc_msgoutq; /* What messages have been sent so far? */
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u_char sc_omess[ESP_MAX_MSG_LEN];
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caddr_t sc_omp; /* Message pointer (for multibyte messages) */
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size_t sc_omlen;
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u_char sc_imess[ESP_MAX_MSG_LEN + 1];
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caddr_t sc_imp; /* Message pointer (for multibyte messages) */
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size_t sc_imlen;
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/* hardware/openprom stuff */
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int sc_node; /* PROM node ID */
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int sc_freq; /* Freq in HZ */
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#ifdef SPARC_DRIVER
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int sc_pri; /* SBUS priority */
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#endif
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int sc_id; /* our scsi id */
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int sc_rev; /* esp revision */
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int sc_minsync; /* minimum sync period / 4 */
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int sc_maxxfer; /* maximum transfer size */
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};
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/* values for sc_state */
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#define ESP_IDLE 1 /* waiting for something to do */
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#define ESP_SELECTING 2 /* SCSI command is arbiting */
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#define ESP_RESELECTED 3 /* Has been reselected */
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#define ESP_CONNECTED 4 /* Actively using the SCSI bus */
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#define ESP_DISCONNECT 5 /* MSG_DISCONNECT received */
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#define ESP_CMDCOMPLETE 6 /* MSG_CMDCOMPLETE received */
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#define ESP_CLEANING 7
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#define ESP_SBR 8 /* Expect a SCSI RST because we commanded it */
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/* values for sc_flags */
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#define ESP_DROP_MSGI 0x01 /* Discard all msgs (parity err detected) */
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#define ESP_ABORTING 0x02 /* Bailing out */
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#define ESP_DOINGDMA 0x04 /* The FIFO data path is active! */
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#define ESP_SYNCHNEGO 0x08 /* Synch negotiation in progress. */
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#define ESP_ICCS 0x10 /* Expect status phase results */
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#define ESP_WAITI 0x20 /* Waiting for non-DMA data to arrive */
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#define ESP_ATN 0x40 /* ATN asserted */
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/* values for sc_msgout */
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#define SEND_DEV_RESET 0x01
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#define SEND_PARITY_ERROR 0x02
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#define SEND_INIT_DET_ERR 0x04
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#define SEND_REJECT 0x08
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#define SEND_IDENTIFY 0x10
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#define SEND_ABORT 0x20
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#define SEND_SDTR 0x40
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#define SEND_WDTR 0x80
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/* SCSI Status codes */
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#define ST_MASK 0x3e /* bit 0,6,7 is reserved */
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/* phase bits */
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#define IOI 0x01
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#define CDI 0x02
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#define MSGI 0x04
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/* Information transfer phases */
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#define DATA_OUT_PHASE (0)
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#define DATA_IN_PHASE (IOI)
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#define COMMAND_PHASE (CDI)
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#define STATUS_PHASE (CDI|IOI)
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#define MESSAGE_OUT_PHASE (MSGI|CDI)
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#define MESSAGE_IN_PHASE (MSGI|CDI|IOI)
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#define PHASE_MASK (MSGI|CDI|IOI)
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/* Some pseudo phases for getphase()*/
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#define BUSFREE_PHASE 0x100 /* Re/Selection no longer valid */
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#define INVALID_PHASE 0x101 /* Re/Selection valid, but no REQ yet */
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#define PSEUDO_PHASE 0x100 /* "pseudo" bit */
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/*
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* Macros to read and write the chip's registers.
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*/
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#ifdef SPARC_DRIVER
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#define ESP_READ_REG(sc, reg) \
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((sc)->sc_reg[(reg) * 4])
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#define ESP_WRITE_REG(sc, reg, val) \
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do { \
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u_char v = (val); \
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(sc)->sc_reg[(reg) * 4] = v; \
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} while (0)
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#else /* ! SPARC_DRIVER */
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#ifdef MAC68K_DRIVER
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#define ESP_READ_REG(sc, reg) \
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((sc)->sc_reg[(reg) * 16])
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#define ESP_WRITE_REG(sc, reg, val) \
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do { \
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u_char v = (val); \
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(sc)->sc_reg[(reg) * 16] = v; \
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} while (0)
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#else
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#if 1
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static inline u_char
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ESP_READ_REG(sc, reg)
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struct esp_softc *sc;
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int reg;
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{
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u_char v;
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v = sc->sc_reg[reg * 2] & 0xff;
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alpha_mb();
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return v;
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}
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#else
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#define ESP_READ_REG(sc, reg) \
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((u_char)((sc)->sc_reg[(reg) * 2] & 0xff))
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#endif
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#define ESP_WRITE_REG(sc, reg, val) \
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do { \
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u_char v = (val); \
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(sc)->sc_reg[(reg) * 2] = v; \
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alpha_mb(); \
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} while (0)
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#endif /* MAC68K_DRIVER */
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#endif /* SPARC_DRIVER */
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#ifdef ESP_DEBUG
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#define ESPCMD(sc, cmd) do { \
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if (esp_debug & ESP_SHOWCCMDS) \
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printf("<cmd:0x%x>", (unsigned)cmd); \
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sc->sc_lastcmd = cmd; \
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ESP_WRITE_REG(sc, ESP_CMD, cmd); \
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} while (0)
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#else
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#define ESPCMD(sc, cmd) ESP_WRITE_REG(sc, ESP_CMD, cmd)
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#endif
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#define SAME_ESP(sc, bp, ca) \
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((bp->val[0] == ca->ca_slot && bp->val[1] == ca->ca_offset) || \
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(bp->val[0] == -1 && bp->val[1] == sc->sc_dev.dv_unit))
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#ifndef SPARC_DRIVER
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#ifdef MAC68K_DRIVER
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/* DMA macros for ESP */
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#define DMA_ISINTR(sc) (ESP_READ_REG((sc)->sc_esp, ESP_STAT) & 0x80)
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#define DMA_RESET(sc) do { (sc)->sc_active = 0; \
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(sc)->sc_tc = 0;} while(0)
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#define DMA_INTR(sc) dma_intr(sc)
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#define DMA_SETUP(sc, paddr, plen, datain, pdmasize) \
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do { \
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(sc)->sc_dmaaddr = paddr; \
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(sc)->sc_pdmalen = plen; \
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(sc)->sc_datain = datain; \
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(sc)->sc_dmasize = *pdmasize; \
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(sc)->sc_tc = 0; \
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} while (0)
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#define DMA_GO(sc) \
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do { \
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if ((sc)->sc_datain == 0) { \
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ESP_WRITE_REG((sc)->sc_esp, \
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ESP_FIFO, **(sc)->sc_dmaaddr); \
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(*(sc)->sc_pdmalen)--; \
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(*(sc)->sc_dmaaddr)++; \
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} \
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(sc)->sc_active = 1; \
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} while (0)
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#define DMA_ISACTIVE(sc) ((sc)->sc_active)
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#else MAC68K_DRIVER
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/* DMA macros for ESP */
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#define DMA_ISINTR(sc) tcds_dma_isintr(sc)
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#define DMA_RESET(sc) tcds_dma_reset(sc)
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#define DMA_INTR(sc) tcds_dma_intr(sc)
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#define DMA_SETUP(sc, addr, len, datain, dmasize) \
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tcds_dma_setup(sc, addr, len, datain, dmasize)
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#define DMA_GO(sc) tcds_dma_go(sc)
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#define DMA_ISACTIVE(sc) tcds_dma_isactive(sc)
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#endif /* MAC68K_DRIVER */
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#endif /* SPARC_DRIVER */
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