216 lines
7.8 KiB
C
216 lines
7.8 KiB
C
/* $NetBSD: isa_shark_machdep.c,v 1.5 1999/09/17 19:59:39 thorpej Exp $ */
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/*
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* Copyright 1997
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* Digital Equipment Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and conditions.
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* Subject to these conditions, you may download, copy, install,
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* use, modify and distribute this software in source and/or binary
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* form. No title or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions as
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* they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or logo of
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* Digital Equipment Corporation. Neither the "Digital Equipment
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* Corporation" name nor any trademark or logo of Digital Equipment
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* Corporation may be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Digital Equipment Corporation.
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*
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* 3) This software is provided "AS-IS" and any express or implied
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* warranties, including but not limited to, any implied warranties
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* of merchantability, fitness for a particular purpose, or
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* non-infringement are disclaimed. In no event shall DIGITAL be
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* liable for any damages whatsoever, and in particular, DIGITAL
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* shall not be liable for special, indirect, consequential, or
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* incidental damages or damages for lost profits, loss of
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* revenue or loss of use, whether such damages arise in contract,
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* negligence, tort, under statute, in equity, at law or otherwise,
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* even if advised of the possibility of such damage.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/syslog.h>
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#include <sys/device.h>
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#include <sys/malloc.h>
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#include <machine/irqhandler.h>
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#include <machine/pio.h>
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#include <dev/isa/isareg.h>
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#include <dev/isa/isavar.h>
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#include <dev/isa/isadmavar.h>
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#include <arm32/isa/icu.h>
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#include <machine/ofw.h>
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struct arm32_isa_chipset isa_chipset_tag;
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unsigned i8259_mask;
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/* Notes on the interaction of StrongARM and ISA. A lot of the nastiness
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is caused by consciously prostituting shark to a low bill of materials.
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It takes on the order of 700ns (about 150 instruction cycles at
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233 MHz) to access the ISA bus, so it is important to minimize the number
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of ISA accesses, in particular to the 8259 interrupt controllers.
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To reduce the number of accesses, the 8259's are NOT run in the
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same mode as on a typical Intel (IBM AT) system, which requires
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an interrupt acknowledge sequence (INTA) for every interrupt.
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Instead, the 8259's are used as big OR gates with interrupt masks
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on the front. The code in irq.S takes particular care to cache
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the state of the interrupt masks and only update them when absolutely
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necessary.
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Unfortunately, resetting the 8259 edge detectors without a real
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INTA sequence is problematic at best. To complicate matters further,
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(unlike EISA components) the 8259s on the Sequoia core logic do
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not allow configuration of edge vs. level on an IRQ-by-IRQ basis.
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Thus, all interrupts must be either edge-triggered or level-triggered.
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To preserve the sanity of the system, this code chooses the
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level-triggered configuration.
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None of the possible operation modes of the 8254 interval timers can
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be used to generate a periodic, level-triggered, clearable clock
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interrupt. This restriction means that TIMER0 -- hardwired to IRQ0 --
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may not be used as the heartbeat timer, as it is on Intel-based PCs.
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Instead, the real-time clock (RTC) interrupt -- connected to
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IRQ8 -- has the right properties and is used for the heartbeat interrupt.
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TIMER0 may still be used to implement a microsecond timer.
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See clock.c for details.
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As on most PC systems, 8254 TIMER1 is used for the ISA refresh signal.
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Unlike most PC systems, 8254 TIMER2 is not used for cheap tone
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generation. Instead, it is used to create a high-availability interrupt
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for bit-bashing functions (e.g. for SmartCard access). TIMER2 output,
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called "SPKR" on Sequoia 2, is routed back into the SWTCH input on
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Sequoia 1. This input eventually reemerges from Sequoia 1 on the SMI pin,
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which is then converted into the StrongARM FIQ (fast interrupt request).
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To clear this interrupt, the StrongARM clears the SMI.
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See .../shark/fiq.S for details.
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One more complication: ISA devices can be rather nasty with respect
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to ISA bus usage. For example, the CS8900 ethernet chip will occupy
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the bus for very long DMA streams. It is possible to configure the
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chip so it relinquishes the ISA bus every 28 usec or so
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(about every 6500 instructions). This causes problems when trying
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to run the TIMER2/SMI/FIQ at 50 kHz, which is required to detect the
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baud rate of the SmartCard. A modification to .../dev/isa/isadma.c
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allows the processor to freeze DMA during critial periods of time.
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This is a working -- but not very satisfactory -- solution to the problem.
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*/
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/*
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* Initialize the interrupt controllers.
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*/
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void
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isa_init8259s()
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{
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/* initialize 8259's */
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outb(IO_ICU1, 0x19); /* reset; four bytes, level triggered */
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outb(IO_ICU1+1, ICU_OFFSET); /* int base: not used */
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outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */
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outb(IO_ICU1+1, 2 | 1); /* auto EOI, 8086 mode */
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outb(IO_ICU1+1, 0xff); /* disable all interrupts */
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outb(IO_ICU1, 0x68); /* special mask mode (if available) */
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outb(IO_ICU1, 0x0a); /* Read IRR, not ISR */
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outb(IO_ICU2, 0x19); /* reset; four bytes, level triggered */
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outb(IO_ICU2+1, ICU_OFFSET+8); /* int base + offset for master: not used */
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outb(IO_ICU2+1, IRQ_SLAVE); /* who ami i? */
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outb(IO_ICU2+1, 2 | 1); /* auto EOI, 8086 mode */
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outb(IO_ICU2+1, 0xff); /* disable all interrupts */
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outb(IO_ICU2, 0x68); /* special mask mode (if available) */
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outb(IO_ICU2, 0x0a); /* Read IRR by default. */
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i8259_mask = 0x0000ffff; /* everything disabled */
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}
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#define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2)
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/*
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* Set up an interrupt handler to start being called.
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*/
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void *
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isa_intr_establish(ic, irq, type, level, ih_fun, ih_arg)
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isa_chipset_tag_t ic;
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int irq;
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int type;
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int level;
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int (*ih_fun) __P((void *));
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void *ih_arg;
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{
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irqhandler_t *ih;
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/* no point in sleeping unless someone can free memory. */
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ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK);
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if (ih == NULL)
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panic("isa_intr_establish: can't malloc handler info");
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if (!LEGAL_IRQ(irq) || type == IST_NONE)
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panic("intr_establish: bogus irq or type");
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/* Note: sequoia doesn't allow configuration of edge vs. level
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on an IRQ-by-IRQ basis. */
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if (type != IST_LEVEL)
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printf("WARNING: irq %d not level triggered\n", irq);
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memset(ih, 0, sizeof *ih);
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ih->ih_func = ih_fun;
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ih->ih_arg = ih_arg;
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ih->ih_level = level;
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ih->ih_name = "isa intr";
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if (irq_claim(irq, ih) == -1)
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panic("isa_intr_establish: can't install handler");
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return (ih);
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}
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/*
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* Deregister an interrupt handler.
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*/
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void
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isa_intr_disestablish(ic, arg)
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isa_chipset_tag_t ic;
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void *arg;
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{
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panic("isa_intr_disestablish");
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}
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/* isa_init() might eventually become the ISA attach routine */
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void
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isa_init(vm_offset_t isa_io_addr, vm_offset_t isa_mem_addr)
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{
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/* initialize the bus space functions */
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isa_io_init(isa_io_addr, isa_mem_addr);
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/* Clear the IRQ/FIQ masks */
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isa_init8259s();
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/* Initialize the ISA interrupt handling code */
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irq_init();
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}
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void
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isa_attach_hook(parent, self, iba)
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struct device *parent, *self;
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struct isabus_attach_args *iba;
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{
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/*
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* Since we can only have one ISA bus, we just use a single
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* statically allocated ISA chipset structure. Pass it up
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* now.
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*/
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iba->iba_ic = &isa_chipset_tag;
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}
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