252 lines
11 KiB
C
252 lines
11 KiB
C
/* $NetBSD: pcctworeg.h,v 1.3 1999/02/20 00:11:59 scw Exp $ */
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/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Steve C. Woodford
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCCchip2 at $FFF42000
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*/
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#ifndef __mvme68k_pcctworeg_h
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#define __mvme68k_pcctworeg_h
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#define PCCTWO_BASE 0xfff42000 /* Phys Addr of PCCchip2 space */
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#define PCCTWO_REG_OFF 0x0000 /* Offset of PCCchip2 registers */
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#define PCCTWO_LPT_OFF 0x0000 /* Offset of parallel port registers */
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#define PCCTWO_MEMC_OFF 0x1000 /* Offset of Memory Controller's regs */
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#define PCCTWO_SCC_OFF 0x3000 /* Offset of CD2401 Serial Comms chip */
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#define PCCTWO_IE_OFF 0x4000 /* Offset of 82596 LAN controller */
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#define PCCTWO_NCRSC_OFF 0x5000 /* Offset of NCR53C710 SCSI chip */
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#define PCCTWO_CLOCK_OFF 0x7e000 /* Offset of MK48T18 NVRAM */
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#define PCCTWO_RTC_OFF 0x1ff8 /* Offset of MK48T18 RTC registers */
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#define PCCTWO_PADDR(off) ((void *)(PCCTWO_BASE + (off)))
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/*
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* The PCCchip2 space is permanently mapped by pmap_bootstrap(). This
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* macro translates PCCTWO offsets into the corresponding KVA.
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*/
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#define PCCTWO_VADDR(off) ((void *)IIOV(PCCTWO_BASE + (off)))
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/*
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* The layout of the PCCchip2's Registers
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*/
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struct pcctwo {
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volatile u_char chip_id; /* Chip ID Register */
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volatile u_char chip_rev; /* Chip Revision Register */
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volatile u_char gen_ctrl; /* General Control Register */
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volatile u_char vector_base; /* Vector Base Register */
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volatile u_long tt1_compare; /* Tick Timer 1 Compare Register */
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volatile u_long tt1_counter; /* Tick Timer 1 Counter Register */
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volatile u_long tt2_compare; /* Tick Timer 2 Compare Register */
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volatile u_long tt2_counter; /* Tick Timer 2 Counter Register */
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volatile u_char prescale_cnt; /* Prescaler Count Register */
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volatile u_char prescale_adj; /* Prescaler Clock Adjust Register */
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volatile u_char tt2_ctrl; /* Tick Timer 2 Control Register */
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volatile u_char tt1_ctrl; /* Tick Timer 1 Control Register */
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volatile u_char gp_in_icr; /* GP Input Interrupt Control Reg. */
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volatile u_char gpio_ctrl; /* GP Input/Output Control Register */
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volatile u_char tt2_icr; /* Tick Timer 2 Interrupt Control Reg */
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volatile u_char tt1_icr; /* Tick Timer 1 Interrupt Control Reg */
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volatile u_char scc_err_sr; /* SCC Error Status Register */
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volatile u_char scc_mod_icr; /* SCC Modem Interrupt Control Reg. */
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volatile u_char scc_tx_icr; /* SCC Transmit Interrupt Control Reg */
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volatile u_char scc_rx_icr; /* SCC Receive Interrupt Control Reg */
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volatile u_char resvd1[3];
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volatile u_char scc_mod_piack; /* SCC Modem PIACK Register */
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volatile u_char resvd2;
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volatile u_char scc_tx_piack; /* SCC Transmit PIACK Register */
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volatile u_char resvd3;
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volatile u_char scc_rx_piack; /* SCC Receive PIACK Register */
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volatile u_char lanc_err_sr; /* LANC Error Status Register */
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volatile u_char resvd4;
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volatile u_char lanc_icr; /* LANC Interrupt Control Register */
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volatile u_char lanc_berr_sr; /* LANC Bus Error Interrupt Ctrl Reg */
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volatile u_char scsi_err_sr; /* SCSI Error Status Register */
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volatile u_char resvd5[2];
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volatile u_char scsi_icr; /* SCSI Interrupt Control Register */
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volatile u_char prt_ack_icr; /* Printer ACK Interrupt Control Reg */
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volatile u_char prt_fault_icr; /* Printer FAULT Interrupt Ctrl Reg */
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volatile u_char prt_sel_icr; /* Printer SEL Interrupt Control Reg */
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volatile u_char prt_pe_icr; /* Printer PE Interrupt Control Reg */
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volatile u_char prt_busy_icr; /* Printer BUSY Interrupt Control Reg */
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volatile u_char resvd6;
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volatile u_char prt_input_sr; /* Printer Input Status Register */
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volatile u_char prt_ctrl; /* Printer Port Control Register */
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volatile u_short chip_speed; /* Chip Speed Register */
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volatile u_short prt_data; /* Printer Data Register */
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volatile u_char resvd7[2];
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volatile u_char irq_level; /* Interrupt Priority Level Register */
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volatile u_char irq_mask; /* Interrupt Mask Register */
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};
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/*
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* Pointer to PCCChip2's Registers. Set up during system boot.
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*/
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extern struct pcctwo *sys_pcctwo;
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/*
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* We use the interrupt vector bases suggested in the Motorola Docs...
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* The first is written to the PCCChip2 for interrupt sources under
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* its control. The second is written to the CD2401's Local Interrupt
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* Vector Register. Thus, we don't use the Auto-Vector facilities
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* for the CD2401, as recommended in the PCCChip2 Programmer's Guide.
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*/
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#define PCCTWO_VECBASE 0x50
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#define PCCTWO_SCC_VECBASE 0x5c
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/*
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* Vector Encoding (Offsets from PCCTWO_VECBASE)
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* The order 0x0 -> 0xf also indicates priority, with 0x0 lowest.
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*/
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#define PCCTWOV_PRT_BUSY 0x0 /* Printer Port 'BSY' */
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#define PCCTWOV_PRT_PE 0x1 /* Printer Port 'PE' (Paper Empty) */
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#define PCCTWOV_PRT_SELECT 0x2 /* Printer Port 'SELECT' */
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#define PCCTWOV_PRT_FAULT 0x3 /* Printer Port 'FAULT' */
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#define PCCTWOV_PRT_ACK 0x4 /* Printer Port 'ACK' */
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#define PCCTWOV_SCSI 0x5 /* SCSI Interrupt */
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#define PCCTWOV_LANC_ERR 0x6 /* LAN Controller Error */
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#define PCCTWOV_LANC_IRQ 0x7 /* LAN Controller Interrupt */
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#define PCCTWOV_TIMER2 0x8 /* Tick Timer 2 Interrupt */
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#define PCCTWOV_TIMER1 0x9 /* Tick Timer 1 Interrupt */
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#define PCCTWOV_GPIO 0xa /* General Purpose Input Interrupt */
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#define PCCTWOV_SCC_RX_EXCEP 0xc /* SCC Receive Exception */
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#define PCCTWOV_SCC_MODEM 0xd /* SCC Modem (Non-Auto-vector mode) */
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#define PCCTWOV_SCC_TX 0xe /* SCC Tx (Non-Auto-vector mode) */
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#define PCCTWOV_SCC_RX 0xf /* SCC Rx (Non-Auto-vector mode) */
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#define PCCTWOV_MAX 16
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/*
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* Bit Values for the General Control Register (sys_pcctwo->gen_ctrl)
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*/
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#define PCCTWO_GEN_CTRL_FAST (1u<<0) /* BBRAM Speed Control */
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#define PCCTWO_GEN_CTRL_MIEN (1u<<1) /* Master Interrupt Enable */
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#define PCCTWO_GEN_CTRL_C040 (1u<<2) /* Set when CPU is mc68k family */
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#define PCCTWO_GEN_CTRL_DR0 (1u<<3) /* Download ROM at 0 (mvme166 only) */
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/*
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* Calculate the Prescaler Adjust value for a given
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* value of BCLK in MHz. (sys_pcctwo->prescale_adj)
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*/
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#define PCCTWO_PRES_ADJ(mhz) (256 - (mhz))
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/*
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* Calculate the Tick Timer Compare register value for
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* a given number of micro-seconds. With the PCCChip2,
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* this is simple since the Tick Counters already have
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* a 1uS period. (sys_pcctwo->tt[12]_compare)
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*/
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#define PCCTWO_US2LIM(us) (us)
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/*
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* The Tick Timer Control Registers (sys_pcctwo->tt[12]_ctrl)
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*/
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#define PCCTWO_TT_CTRL_CEN (1u<<0) /* Counter Enable */
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#define PCCTWO_TT_CTRL_COC (1u<<1) /* Clear On Compare */
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#define PCCTWO_TT_CTRL_COVF (1u<<2) /* Clear Overflow Counter */
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#define PCCTWO_TT_CTRL_OVF(r) ((r)>>4)/* Value of the Overflow Counter */
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/*
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* All the Interrupt Control Registers on the PCCChip2 mostly
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* share the same basic layout. These are defined as follows:
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*/
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#define PCCTWO_ICR_LEVEL_MASK 0x7 /* Mask for the interrupt level */
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#define PCCTWO_ICR_ICLR (1u<<3) /* Clear Int. (edge-sensitive mode) */
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#define PCCTWO_ICR_AVEC (1u<<3) /* Enable Auto-Vector Mode */
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#define PCCTWO_ICR_IEN (1u<<4) /* Interrupt Enable */
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#define PCCTWO_ICR_INT (1u<<5) /* Interrupt Active */
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#define PCCTWO_ICR_LEVEL (0u<<6) /* Level Triggered */
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#define PCCTWO_ICR_EDGE (1u<<6) /* Edge Triggered */
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#define PCCTWO_ICR_RISE_HIGH (0u<<7) /* Polarity: Rising Edge or Hi Level */
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#define PCCTWO_ICR_FALL_LOW (1u<<7) /* Polarity: Falling Edge or Lo Level */
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#define PCCTWO_ICR_SC_RD(r) ((r)>>6)/* Get Snoop Control Bits */
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#define PCCTWO_ICR_SC_WR(r) ((r)<<6)/* Write Snoop Control Bits */
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/*
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* Most of the Error Status Registers (sys_pcctwo->*_err_sr) mostly
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* follow the same layout. These error registers are used when a
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* device (eg. SCC, LANC) is mastering the PCCChip2's local bus (for
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* example, performing a DMA) and some error occurs. The bits are
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* defined as follows:
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*/
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#define PCCTWO_ERR_SR_SCLR (1u<<0) /* Clear Error Status */
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#define PCCTWO_ERR_SR_LTO (1u<<1) /* Local Bus Timeout */
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#define PCCTWO_ERR_SR_EXT (1u<<2) /* External (VMEbus) Error */
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#define PCCTWO_ERR_SR_PRTY (1u<<3) /* DRAM Parity Error */
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#define PCCTWO_ERR_SR_RTRY (1u<<4) /* Retry Required */
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#define PCCTWO_ERR_SR_MASK 0x0Eu
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/*
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* General Purpose Input/Output Pin Control Register
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* (sys_pcctwo->gpio_ctrl)
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*/
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#define PCCTWO_GPIO_CTRL_GPO (1u<<0) /* Controls the GP Output Pin */
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#define PCCTWO_GPIO_CTRL_GPOE (1u<<1) /* General Purpose Output Enable */
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#define PCCTWO_GPIO_CTRL_GPI (1u<<3) /* The current state of the GP Input */
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/*
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* Printer Input Status Register (sys_pcctwo->prt_input_sr)
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*/
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#define PCCTWO_PRT_IN_SR_BSY (1u<<0) /* State of printer's BSY Input */
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#define PCCTWO_PRT_IN_SR_PE (1u<<1) /* State of printer's PE Input */
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#define PCCTWO_PRT_IN_SR_SEL (1u<<2) /* State of printer's SELECT Input */
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#define PCCTWO_PRT_IN_SR_FLT (1u<<3) /* State of printer's FAULT Input */
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#define PCCTWO_PRT_IN_SR_ACK (1u<<4) /* State of printer's ACK Input */
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#define PCCTWO_PRT_IN_SR_PINT (1u<<7) /* Printer Interrupt Status */
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/*
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* Printer Port Control Register (sys_pcctwo->prt_ctrl)
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*/
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#define PCCTWO_PRT_CTRL_MAN (1u<<0) /* Manual Strobe Control */
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#define PCCTWO_PRT_CTRL_FAST (1u<<1) /* Fast Auto Strobe */
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#define PCCTWO_PRT_CTRL_STB (1u<<2) /* Strobe Pin, in manual control mode */
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#define PCCTWO_PRT_CTRL_INP (1u<<3) /* Printer Input Prime */
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#define PCCTWO_PRT_CTRL_DOEN (1u<<4) /* Printer Data Output Enable */
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#endif /* __mvme68k_pcctworeg_h */
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