168 lines
5.6 KiB
C
168 lines
5.6 KiB
C
/* $NetBSD: pccreg.h,v 1.5 1996/09/12 04:54:19 thorpej Exp $ */
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/*
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*
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* Copyright (c) 1995 Charles D. Cranor
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Charles D. Cranor.
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* peripheral channel controller (at pa fffe0000)
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*/
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#define PCC_BASE 0xfffe0000 /* PA of PCC chip space */
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#define PCC_CLOCK_OFF 0x0000 /* offset of Mostek clock chip */
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#define PCC_RTC_OFF 0x07f8 /* offset of clock registers in MK */
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#define PCC_REG_OFF 0x1000 /* offset of PCC chip registers */
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#define PCC_LE_OFF 0x1800 /* offset of LANCE ethernet chip */
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#define PCC_VME_OFF 0x2000 /* offset of VME chip */
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#define PCC_LPT_OFF 0x2800 /* offset of parallel port register */
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#define PCC_ZS0_OFF 0x3000 /* offset of first 8530 UART */
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#define PCC_ZS1_OFF 0x3800 /* offset of second 8530 UART */
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#define PCC_WDSC_OFF 0x4000 /* offset of 33c93 SCSI chip */
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#define PCC_PADDR(off) ((void *)(PCC_BASE + (off)))
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/*
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* The PCC space is permanently mapped by pmap_bootstrap(). This
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* macro translates PCC offsets into the corresponding KVA.
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*/
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#define PCC_VADDR(off) ((void *)IIOV(PCC_BASE + (off)))
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struct pcc {
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volatile u_long dma_taddr; /* dma table address */
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volatile u_long dma_daddr; /* dma data address */
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volatile u_long dma_bcnt; /* dma byte count */
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volatile u_long dma_hold; /* dma data hold register */
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volatile u_short t1_pload; /* timer1 preload */
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volatile u_short t1_count; /* timer1 count */
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volatile u_short t2_pload; /* timer2 preload */
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volatile u_short t2_count; /* timer2 count */
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volatile u_char t1_int; /* timer1 interrupt ctrl */
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volatile u_char t1_cr; /* timer1 ctrl reg */
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volatile u_char t2_int; /* timer2 interrupt ctrl */
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volatile u_char t2_cr; /* timer2 ctrl reg */
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volatile u_char acf_int; /* acfail intr reg */
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volatile u_char dog_int; /* watchdog intr reg */
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volatile u_char pr_int; /* printer intr reg */
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volatile u_char pr_cr; /* printer ctrl */
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volatile u_char dma_int; /* dma interrupt control */
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volatile u_char dma_csr; /* dma csr */
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volatile u_char bus_int; /* bus error interrupt */
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volatile u_char dma_sr; /* dma status register */
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volatile u_char abrt_int; /* abort interrupt control reg */
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volatile u_char ta_fcr; /* table address function code reg */
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volatile u_char zs_int; /* serial interrupt reg */
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volatile u_char gen_cr; /* general control register */
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volatile u_char le_int; /* ethernet interrupt */
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volatile u_char gen_sr; /* general status */
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volatile u_char scsi_int; /* scsi interrupt reg */
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volatile u_char slave_ba; /* slave base addr reg */
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volatile u_char sw1_int; /* software interrupt #1 cr */
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volatile u_char int_vectr; /* interrupt base vector register */
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volatile u_char sw2_int; /* software interrupt #2 cr */
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volatile u_char pcc_rev; /* revision level */
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};
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/*
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* points to system's PCC
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*/
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extern struct pcc *sys_pcc;
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/*
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* we lock off our interrupt vector at 0x40.
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*/
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#define PCC_VECBASE 0x40
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#define PCC_NVEC 12
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/*
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* vectors we use
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*/
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#define PCCV_ACFAIL 0
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#define PCCV_BERR 1
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#define PCCV_ABORT 2
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#define PCCV_ZS 3
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#define PCCV_LE 4
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#define PCCV_SCSIP 5
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#define PCCV_SCSID 6
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#define PCCV_PRINTER 7
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#define PCCV_TIMER1 8
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#define PCCV_TIMER2 9
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#define PCCV_SOFT1 10
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#define PCCV_SOFT2 11
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/*
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* enable interrupt
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*/
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#define PCC_ICLEAR 0x80
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#define PCC_IENABLE 0x08
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/*
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* interrupt mask
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*/
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#define PCC_IMASK 0x7
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/*
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* clock/timer
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*/
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#define PCC_TIMERACK 0x80 /* ack intr */
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#define PCC_TIMER100HZ 63936 /* load value for 100Hz */
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#define PCC_TIMERCLEAR 0x0 /* reset and clear timer */
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#define PCC_TIMERSTOP 0x1 /* stop clock, but don't clear it */
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#define PCC_TIMERSTART 0x3 /* start timer */
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#define pcc_timer_hz2lim(hz) (65536 - (160000/(hz)))
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#define pcc_timer_us2lim(us) (65536 - (160000/(1000000/(us))))
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/*
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* serial control
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*/
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#define PCC_ZSEXTERN 0x10 /* let PCC supply vector */
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/*
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* abort switch
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*/
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#define PCC_ABORT_IEN 0x08 /* enable interrupt */
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#define PCC_ABORT_ABS 0x40 /* current state of switch */
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#define PCC_ABORT_ACK 0x80 /* interrupt active; write to ack */
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/*
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* general control register
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*/
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#define PCC_GENCR_IEN 0x10 /* global interrupt enable */
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