283 lines
10 KiB
C
283 lines
10 KiB
C
/* $NetBSD: ixp12x0reg.h,v 1.6 2005/12/11 12:16:50 christos Exp $ */
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/*
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* Copyright (c) 2002, 2003
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* Ichiro FUKUHARA <ichiro@ichiro.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Ichiro FUKUHARA.
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* 4. The name of the company nor the name of the author may be used to
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* endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY ICHIRO FUKUHARA ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL ICHIRO FUKUHARA OR THE VOICES IN HIS HEAD BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _IXP12X0REG_H_
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#define _IXP12X0REG_H_
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/*
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* Physical memory map for the Intel IXP12X0
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*/
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/*
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* FFFF FFFF ---------------------------
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* Device 6
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* SDRAM
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* FF00 0000 - FF00 0014
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* SDRAM Control Register
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* D000 0000 - DFFF FFFF
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* Prefetch 256MB
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* C000 0000 - CFFF FFFF
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* non-Prefetch 256MB
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* C000 0000 ---------------------------
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* Device 5
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* AMBA Translation (ATU)
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* B000 0000 ---------------------------
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* Device 4
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* Reserved
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* A000 0000 ---------------------------
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* Device 3
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* StrongARM Core System
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* 9000 0000 ---------------------------
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* Device 2
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* Reserved
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* 8000 0000 ---------------------------
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* Device 1
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* PCI UNIT
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* 6000 0000 - 7FFF FFFF
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* PCI Memory Cycle Access
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* 5400 0000 - 5400 FFFF
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* PCI I/O Cycle Access
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* 5300 0000 - 53BF FFFF
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* PCI Type0 Configuration Cycle Access
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* 5200 0000 - 52FF FFFF
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* PCI Type1 Configuration Cycle Access
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* 4200 0000 - 4200 03FF
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* Local PCI Configuration Space
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* 4000 0000 ---------------------------
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* Device 0
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* SRAM UNIT
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* 0000 0000 ---------------------------
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*/
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/*
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* Virtual memory map for the Intel IXP12X0 integrated devices
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*
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* IXP12x0 processors have many device registers at very lower addresses.
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* To make user process space wider, we map the registers at lower address
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* to upper address using address translation of virtual memory system.
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*
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* Some device registers are staticaly mapped on upper address region.
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* because we have to access them before bus_space is initialized.
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* Most device is dinamicaly mapped by bus_space_map(). In this case,
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* the actual mapped (virtual) address are not cared by device drivers.
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*/
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/*
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* FFFF FFFF ---------------------------
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*
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* F400 0000 ---------------------------
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* PCI Type 0 Configuration Cycle Access
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* VA F300 0000 == PA 5300 0000 (16Mbyte)
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* F300 0000 ---------------------------
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* PCI Type 1 Configuration Cycle Access
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* VA F200 0000 == PA 5200 0000 (16Mbyte)
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* F200 0000 ---------------------------
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* not used
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* F020 0000 ---------------------------
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* PCI Registers Accessible Through I/O
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* VA F010 0000 == PA 5400 0000 (1Mbyte)
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* F010 0000 ---------------------------
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* not used
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* F001 1000 ---------------------------
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* PCI Registers Accessible Through StrongARM Core
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* VA F001 0000 == PA 4200 0000 (4kbyte)
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* F001 0300 - F001 036F TIMER
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* F001 0200 - F001 0293 PCI_FIQ
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* F001 0180 - F001 0193 PCI_IRQ
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* F001 0000 ---------------------------
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* StrongARM System and Peripheral Registers
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* VA F000 0000 == PA 9000 0000 (64kbyte)
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* F000 3400 - F000 3C03 UART
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* F000 3400 - F000 3C03 UART
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* F000 2000 - F000 3003 RTC
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* F000 1C00 - F000 1C03 GPIO_DATA
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* F000 1800 - F000 1C03 GPIO
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* F000 1400 - F000 1403 IRQ
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* F000 1000 - F000 1003 FIQ
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* F000 0C00 - F000 0C03 PLL_CFG (not used at this addres)
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* F000 0000 ---------------------------
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* Kernel text and data
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* C000 0000 ---------------------------
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* L2 tables for user process (XXX should be fixed)
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* 8000 0000 ---------------------------
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* PCI Registers Accessible Through Memory
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* VA 6000 0000 == PA 6000 0000 (512Mbyte)
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* 6000 0000 ---------------------------
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* 5400 0000 ---------------------------
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* 0000 0000 ---------------------------
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*
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*/
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/* Virtual address for I/O space */
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#define IXP12X0_IO_VBASE 0xf0000000UL
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/* StrongARM System and Peripheral Registers */
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#define IXP12X0_SYS_VBASE 0xf0000000UL
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#define IXP12X0_SYS_HWBASE 0x90000000UL
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#define IXP12X0_SYS_SIZE 0x00010000UL /* 64Kbyte */
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#define IXP12X0_PLL_CFG (IXP12X0_IO_VBASE + 0x0c00)
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#define IXP12X0_PLL_CFG_CCF 0x1f
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/* PCI Registers Accessible Through StrongARM Core */
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#define IXP12X0_PCI_VBASE 0xf0010000UL
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#define IXP12X0_PCI_HWBASE 0x42000000UL
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#define IXP12X0_PCI_SIZE 0x00001000UL /* 4Kbyte */
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/* PCI I/O Space */
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#define IXP12X0_PCI_IO_VBASE 0xf0100000UL
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#define IXP12X0_PCI_IO_HWBASE 0x54000000UL
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#define IXP12X0_PCI_IO_SIZE 0x00100000UL /* 1Mbyte */
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/* PCI Memory Space */
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#define IXP12X0_PCI_MEM_HWBASE 0x60000000UL /* VA == PA */
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#define IXP12X0_PCI_MEM_VBASE IXP12X0_PCI_MEM_HWBASE
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#define IXP12X0_PCI_MEM_SIZE 0x20000000UL
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/* PCI Type0/1 Configuration address */
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#define IXP12X0_PCI_TYPE0_HWBASE 0x53000000UL
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#define IXP12X0_PCI_TYPE0_VBASE 0xf3000000UL
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#define IXP12X0_PCI_TYPE0_SIZE 0x01000000UL /* 16MB */
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#define IXP12X0_PCI_TYPE1_HWBASE 0x52000000UL
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#define IXP12X0_PCI_TYPE1_VBASE 0xf2000000UL
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#define IXP12X0_PCI_TYPE1_SIZE 0x01000000UL /* 16MB */
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/*
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* SlowPort I/O Register
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*/
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/* see. arch/evbarm/ixm1200/ixm1200reg.h */
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/* Physical register base addresses */
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/* #define IXP12X0_GPIO_VBASE */
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#define IXP12X0_GPIO_HWBASE 0x90001800UL
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#define IXP12X0_GPIO_SIZE 0x00000800UL
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/* Interrupts */
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#define IXP12X0_FIQ_VBASE (IXP12X0_IO_VBASE + 0x1000)
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#define IXP12X0_FIQ_HWBASE 0x90001000UL
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#define IXP12X0_FIQ_SIZE 0x00000004UL
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#define IXP12X0_IRQ_VBASE (IXP12X0_IO_VBASE + 0x1400)
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#define IXP12X0_IRQ_HWBASE 0x90001400UL
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#define IXP12X0_IRQ_SIZE 0x00000004UL
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/*
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* Interrupt index assignment
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*
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*
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* FIQ/IRQ bitmap in "StrongARM System and Peripheral Registers"
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-------------------------------------------+-+-+-+-+-+-+-+---+
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* |M| |U|S|R|S|U|C|P| |
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* |B| |A|D|T|R|E|I|C| |
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* |Z| RES |R|R|C|A|N|N|I|RES|
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* | | |T|A| |M|G|T| | |
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* | | | |M| | | | | | |
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* +-+-------------------------------------------+-+-+-+-+-+-+-+---+
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* 3
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* index 1 8 7 6 5 4 3 2
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*
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*
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* We Map a software interrupt queue index to the unused bits in the
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* IRQ/FIQ registers. (in "StrongARM System and Peripheral Registers")
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*
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* XXX will need to revisit this if those bits are ever used in future
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* steppings).
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* bit 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+
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* |M|S|C|N|S| |U|S|R|S|U|C|P| |
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* |B|O|L|E|E| |A|D|T|R|E|I|C| |
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* |Z|F|O|T|R| RES |R|R|C|A|N|N|I|RES|
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* | |T|C| |I| |T|A| |M|G|T| | |
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* | | |K| |A| | |M| | | | | | |
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* | | | | |L| | | | | | | | | |
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* +-+-+-+-+-+-----------------------------------+-+-+-+-+-+-+-+---+
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* 3 3 2 2 2
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* index 1 0 9 8 7 8 7 6 5 4 3 2
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*
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*/
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#define NIRQ 64
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#define SYS_NIRQ 32
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#define IXP12X0_INTR_MBZ 31
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#define IXP12X0_INTR_bit30 30
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#define IXP12X0_INTR_bit29 29
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#define IXP12X0_INTR_bit28 28
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#define IXP12X0_INTR_bit27 27
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#define IXP12X0_INTR_bit26 26
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#define IXP12X0_INTR_bit25 25
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#define IXP12X0_INTR_bit24 24
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#define IXP12X0_INTR_bit23 23
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#define IXP12X0_INTR_bit22 22
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#define IXP12X0_INTR_bit21 21
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#define IXP12X0_INTR_bit20 20
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#define IXP12X0_INTR_bit19 19
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#define IXP12X0_INTR_bit18 18
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#define IXP12X0_INTR_bit17 17
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#define IXP12X0_INTR_bit16 16
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#define IXP12X0_INTR_bit15 15
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#define IXP12X0_INTR_bit14 14
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#define IXP12X0_INTR_bit13 13
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#define IXP12X0_INTR_bit12 12
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#define IXP12X0_INTR_bit11 11
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#define IXP12X0_INTR_bit10 10
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#define IXP12X0_INTR_bit9 9
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#define IXP12X0_INTR_UART 8
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#define IXP12X0_INTR_SDRAM 7
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#define IXP12X0_INTR_RTC 6
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#define IXP12X0_INTR_SRAM 5
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#define IXP12X0_INTR_UENG 4
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#define IXP12X0_INTR_CINT 3
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#define IXP12X0_INTR_PCI 2
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#define IXP12X0_INTR_bit1 1
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#define IXP12X0_INTR_bit0 0
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#define IXP12X0_INTR_MASK \
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((1U << IXP12X0_INTR_MBZ) \
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| (1U << IXP12X0_INTR_UART) \
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| (1U << IXP12X0_INTR_SDRAM) \
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| (1U << IXP12X0_INTR_RTC) \
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| (1U << IXP12X0_INTR_SRAM) \
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| (1U << IXP12X0_INTR_UENG) \
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| (1U << IXP12X0_INTR_CINT))
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#endif /* _IXP12X0REG_H_ */
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