138 lines
5.5 KiB
C
138 lines
5.5 KiB
C
/* $NetBSD: via8231reg.h,v 1.1 2006/01/01 12:12:44 xtraeme Exp $ */
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/* OpenBSD: via8231reg.h,v 1.4 2005/10/26 21:38:28 mickey Exp */
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/*
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* Copyright (c) 2005, by Michael Shalayeff
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* Copyright (c) 2003, by Matthew Gream
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* Copyright (c) 1999, by UCHIYAMA Yasushi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. The name of the developer may NOT be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Register definitions for the VIA8231 PCI to ISA Bridge
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*/
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/*
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* Edge Triggered Interrupt Select register. (0x54)
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* bits 7-4: reserved
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* bit 3: Edge Triggered Interrupt Select for PCI Interrupt A
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* bit 2: Edge Triggered Interrupt Select for PCI Interrupt B
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* bit 1: Edge Triggered Interrupt Select for PCI Interrupt C
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* bit 0: Edge Triggered Interrupt Select for PCI Interrupt D
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* 0 = Non-invert (level)
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* 1 = Invert (edge)
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*
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* PIRQ Select register. (0x55 - 0x57)
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* (0x55)
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* bits 7-4: PINTA# Routing
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* bits 3-0: reserved
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* (0x56)
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* bits 7-4: PINTC# Routing
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* bits 3-0: PINTB# Routing
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* (0x57)
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* bits 7-4: PINTD# Routing
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* bits 3-0: reserved
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* PIRQ Select register. (0x44 - 0x47)
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* (0x44)
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* bits 7-4: PINTF# Routing
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* bits 3-0: PINTE# Routing
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* (0x45)
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* bits 7-4: PINTH# Routing
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* bits 3-0: PINTG# Routing
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* (0x46)
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* bit 4: EFGH/ABCD share (1 -- use above mappings)
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* bit 3: Edge Triggered Interrupt Select for PCI Interrupt H
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* bit 2: Edge Triggered Interrupt Select for PCI Interrupt G
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* bit 1: Edge Triggered Interrupt Select for PCI Interrupt F
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* bit 0: Edge Triggered Interrupt Select for PCI Interrupt E
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*
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* 0000: Disabled 0100: IRQ4 1000: Reserved 1100: IRQ12
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* 0001: IRQ1 0101: IRQ5 1001: IRQ9 1101: Reserved
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* 0010: Reserved 0110: IRQ6 1010: IRQ10 1110: IRQ14
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* 0011: IRQ3 0111: IRQ7 1011: IRQ11 1111: IRQ15
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*/
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#define VIA8231_CFG_PIR 0x54
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#define VIA8237_CFG_PIR 0x44
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#define VIA8231_TRIGGER_CNFG_MASK 0x000000ff
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#define VIA8231_TRIGGER_CNFG_SHFT 0
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#define VIA8237_TRIGGER_CNFG_MASK 0x000f0000
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#define VIA8237_TRIGGER_CNFG_SHFT 16
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#define VIA8231_TRIGGER_CNFG_LEVEL 0
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#define VIA8231_TRIGGER_CNFG_EDGE 1
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#define VIA8237_TRIGGER_CNFG_ENA 0x00100000
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#define VIA8231_GET_TRIGGER(ph) \
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((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
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& VIA8231_TRIGGER_CNFG_MASK) >> VIA8231_TRIGGER_CNFG_SHFT)
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#define VIA8237_GET_TRIGGER(ph) \
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((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
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& VIA8237_TRIGGER_CNFG_MASK) >> VIA8237_TRIGGER_CNFG_SHFT)
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#define VIA8231_SET_TRIGGER(ph, n) \
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pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
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(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
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& ~VIA8231_TRIGGER_CNFG_MASK) | ((n) << VIA8231_TRIGGER_CNFG_SHFT))
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#define VIA8237_SET_TRIGGER(ph, n) \
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pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
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(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
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& ~VIA8237_TRIGGER_CNFG_MASK) | ((n) << VIA8237_TRIGGER_CNFG_SHFT))
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#define VIA8231_ROUTING_CNFG_MASK 0xffffff00
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#define VIA8231_ROUTING_CNFG_SHFT 8 /* skip 0x54 triggers */
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#define VIA8231_ROUTING_CNFG_DISABLED 0
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#define VIA8237_ROUTING_CNFG_MASK 0xffff
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#define VIA8237_ROUTING_CNFG_SHFT 0
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#define VIA8231_GET_ROUTING(ph) \
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((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
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& VIA8231_ROUTING_CNFG_MASK) >> VIA8231_ROUTING_CNFG_SHFT)
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#define VIA8237_GET_ROUTING(ph) \
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((pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
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& VIA8237_ROUTING_CNFG_MASK) >> VIA8237_ROUTING_CNFG_SHFT)
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#define VIA8231_SET_ROUTING(ph, n) \
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pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR, \
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(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8231_CFG_PIR) \
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& ~VIA8231_ROUTING_CNFG_MASK) | ((n) << VIA8231_ROUTING_CNFG_SHFT))
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#define VIA8237_SET_ROUTING(ph, n) \
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pci_conf_write((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR, \
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(pci_conf_read((ph)->ph_pc, (ph)->ph_tag, VIA8237_CFG_PIR) \
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& ~VIA8237_ROUTING_CNFG_MASK) | \
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((n) << VIA8237_ROUTING_CNFG_SHFT) | VIA8237_TRIGGER_CNFG_ENA)
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#define VIA8231_PIRQ_MASK 0xdefa
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#define VIA8231_PIRQ_LEGAL(irq) \
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((irq) >= 0 && (irq) <= 15 && ((1 << (irq)) & VIA8231_PIRQ_MASK))
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#define VIA8231_LINK_MAX 3
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#define VIA8237_LINK_MAX 7
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#define VIA8231_LINK_LEGAL(link) \
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((link) >= 0 && (link) <= VIA8231_LINK_MAX)
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#define VIA8237_LINK_LEGAL(link) \
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((link) >= 0 && (link) <= VIA8237_LINK_MAX)
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#define VIA8231_TRIG_LEGAL(trig) \
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((trig) == IST_LEVEL || (trig) == IST_EDGE)
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