34ab2734da
* add "MIPS_3k_" for the MIPS-I r[23]000-specific register definitions.
* add "MIPS_4k_" for the MIPS-II/III r4000-specific register definitions.
* add #defines that provide the old values for locore and user
code, so the existing code continues to compile.
Regression-tested against the old headers by grepping for #define's,
editing out the defined symbols, and preprocessing with both the previous
machConst.h headers and this version.
Some unused symbols (CPU and FPU must-be-zero constants) are no longer defined.
Pica interrupt masks are now constant expressions instead of constant
values.
TODO:
* factor out the common #defines into src/sys/arch/mips.
* Get rid of the Sprite coding-style names (MACH_xxx).
* Separate out the r3k/r4k differences from the Pica/pmax differences.
* Figure out how to have a run-time choice of r3k vs. r4k support,
instead of a compile-time choice.
585 lines
18 KiB
C
585 lines
18 KiB
C
/* $NetBSD: machConst.h,v 1.5 1996/03/28 11:34:05 jonathan Exp $ */
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/*
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* Ralph Campbell and Rick Macklem.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)machConst.h 8.1 (Berkeley) 6/10/93
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*
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* machConst.h --
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*
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* Machine dependent constants.
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*
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* Copyright (C) 1989 Digital Equipment Corporation.
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* Permission to use, copy, modify, and distribute this software and
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* its documentation for any purpose and without fee is hereby granted,
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* provided that the above copyright notice appears in all copies.
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* Digital Equipment Corporation makes no representations about the
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* suitability of this software for any purpose. It is provided "as is"
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* without express or implied warranty.
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*
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
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* v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
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* v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
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* from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
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* v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
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*/
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#ifndef _MACHCONST
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#define _MACHCONST
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#define MACH_KUSEG_ADDR 0x0
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#define MACH_CACHED_MEMORY_ADDR 0x80000000
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#define MACH_UNCACHED_MEMORY_ADDR 0xa0000000
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#define MACH_KSEG2_ADDR 0xc0000000
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#define MACH_MAX_MEM_ADDR 0xbe000000
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#define MACH_RESERVED_ADDR 0xbfc80000
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#define MACH_CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define MACH_PHYS_TO_CACHED(x) ((unsigned)(x) | MACH_CACHED_MEMORY_ADDR)
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#define MACH_UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff)
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#define MACH_PHYS_TO_UNCACHED(x) ((unsigned)(x) | MACH_UNCACHED_MEMORY_ADDR)
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/* Map virtual address to index in r4k virtually-indexed cache */
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#define MIPS_R4K_VA_TO_CINDEX(x) \
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((unsigned)(x) & 0xffffff | MACH_CACHED_MEMORY_ADDR)
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/* XXX compatibility with Pica port */
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#define MACH_VA_TO_CINDEX(x) MIPS_R4K_VA_TO_CINDEX(x)
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/*
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* XXX
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* Port-specific constants:
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* Kernel virtual address at which kernel is loaded, and
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* Kernel virtual address for user page table entries
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* (i.e., the address for the context register).
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*/
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#ifdef pmax
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#define MACH_CODE_START 0x80030000
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#define VMMACH_PTE_BASE 0xFFC00000
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#endif /* pmax */
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#ifdef pica
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#define MACH_CODE_START 0x80080000
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#define VMMACH_PTE_BASE 0xFF800000
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#endif /* pica */
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/*
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* The bits in the cause register.
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*
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* Bits common to r3000 and r4000:
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*
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* MACH_CR_BR_DELAY Exception happened in branch delay slot.
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* MACH_CR_COP_ERR Coprocessor error.
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* MACH_CR_IP Interrupt pending bits defined below.
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* (same meaning as in CAUSE register).
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* MACH_CR_EXC_CODE The exception type (see exception codes below).
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*
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* Differences:
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* r3k has 4 bits of execption type, r4k has 5 bits.
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*/
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#define MACH_CR_BR_DELAY 0x80000000
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#define MACH_CR_COP_ERR 0x30000000
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#define MIPS_3K_CR_EXC_CODE 0x0000003C
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#define MIPS_4K_CR_EXC_CODE 0x0000007C
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#define MACH_CR_IP 0x0000FF00
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#define MACH_CR_EXC_CODE_SHIFT 2
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#ifdef pmax /* XXX not used any more, only to satisfy regression tests */
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#define MACH_CR_EXC_CODE MIPS_3K_CR_EXC_CODE
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#endif /* pmax */
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#ifdef pica
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#define MACH_CR_EXC_CODE MIPS_4K_CR_EXC_CODE
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#endif /* pica */
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/*
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* The bits in the status register. All bits are active when set to 1.
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*
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* R3000 status register fields:
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* MACH_SR_CO_USABILITY Control the usability of the four coprocessors.
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* MACH_SR_BOOT_EXC_VEC Use alternate exception vectors.
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* MACH_SR_TLB_SHUTDOWN TLB disabled.
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*
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* MIPS_SR_INT_IE Master (current) interrupt enable bit.
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*
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* Differences:
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* r3k has cache control is via frobbing SR register bits, whereas the
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* r4k cache control is via explicit instructions.
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* r3k has a 3-entry stack of kernel/user bits, whereas the
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* r4k has kernel/supervisor/user.
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*/
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#define MACH_SR_COP_USABILITY 0xf0000000
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#define MACH_SR_COP_0_BIT 0x10000000
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#define MACH_SR_COP_1_BIT 0x20000000
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/* r4k and r3k differences, see below */
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#define MACH_SR_BOOT_EXC_VEC 0x00400000
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#define MACH_SR_TLB_SHUTDOWN 0x00200000
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/* r4k and r3k differences, see below */
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#define MIPS_SR_INT_IE 0x00000001
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/*#define MACH_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
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/*#define MACH_SR_INT_MASK 0x0000ff00*/
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#define MACH_SR_INT_ENAB MIPS_SR_INT_IE /* backwards compatibility */
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#define MACH_SR_INT_ENA_CUR MIPS_SR_INT_IE /* backwards compatibility */
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/*
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* The R2000/R3000-specific status register bit definitions.
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* all bits are active when set to 1.
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*
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* MACH_SR_PARITY_ERR Parity error.
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* MACH_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
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* MACH_SR_PARITY_ZERO Zero replaces outgoing parity bits.
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* MACH_SR_SWAP_CACHES Swap I-cache and D-cache.
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* MACH_SR_ISOL_CACHES Isolate D-cache from main memory.
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* Interrupt enable bits defined below.
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* MACH_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
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* MACH_SR_INT_ENA_OLD Old interrupt enable bit.
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* MACH_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
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* MACH_SR_INT_ENA_PREV Previous interrupt enable bit.
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* MACH_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
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*/
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#define MIPS_3K_PARITY_ERR 0x00100000
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#define MIPS_3K_CACHE_MISS 0x00080000
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#define MIPS_3K_PARITY_ZERO 0x00040000
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#define MIPS_3K_SWAP_CACHES 0x00020000
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#define MIPS_3K_ISOL_CACHES 0x00010000
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#define MIPS_3K_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
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#define MIPS_3K_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
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#define MIPS_3K_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
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#define MIPS_3K_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
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#define MIPS_3K_SR_KU_CUR 0x00000002 /* current KU */
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/* backwards compatibility */
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#define MACH_SR_PARITY_ERR MIPS_3K_PARITY_ERR
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#define MACH_SR_CACHE_MISS MIPS_3K_CACHE_MISS
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#define MACH_SR_PARITY_ZERO MIPS_3K_PARITY_ZERO
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#define MACH_SR_SWAP_CACHES MIPS_3K_SWAP_CACHES
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#define MACH_SR_ISOL_CACHES MIPS_3K_ISOL_CACHES
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#define MACH_SR_KU_OLD MIPS_3K_SR_KU_OLD
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#define MACH_SR_INT_ENA_OLD MIPS_3K_SR_INT_ENA_OLD
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#define MACH_SR_KU_PREV MIPS_3K_SR_KU_PREV
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#define MACH_SR_KU_CUR MIPS_3K_SR_KU_CUR
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#define MACH_SR_INT_ENA_PREV MIPS_3K_SR_INT_ENA_PREV
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/*
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* R4000 status register bit definitons,
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* where different from r2000/r3000.
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*/
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#define MIPS_4K_SR_RP 0x08000000
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#define MIPS_4K_SR_FR_32 0x04000000
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#define MIPS_4K_SR_RE 0x02000000
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#define MIPS_4K_SR_SOFT_RESET 0x00100000
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#define MIPS_4K_SR_DIAG_CH 0x00040000
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#define MIPS_4K_SR_DIAG_CE 0x00020000
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#define MIPS_4K_SR_DIAG_PE 0x00010000
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#define MIPS_4K_SR_KX 0x00000080
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#define MIPS_4K_SR_SX 0x00000040
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#define MIPS_4K_SR_UX 0x00000020
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#define MIPS_4K_SR_KSU_MASK 0x00000018
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#define MIPS_4K_SR_KSU_USER 0x00000010
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#define MIPS_4K_SR_KSU_SUPER 0x00000008
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#define MIPS_4K_SR_KSU_KERNEL 0x00000000
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#define MIPS_4K_SR_ERL 0x00000004
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#define MIPS_4K_SR_EXL 0x00000002
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/* backwards compatibility with names used in Pica port */
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#define MACH_SR_RP MIPS_4K_SR_RP
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#define MACH_SR_FR_32 MIPS_4K_SR_FR_32
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#define MACH_SR_RE MIPS_4K_SR_RE
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#define MACH_SR_SOFT_RESET MIPS_4K_SR_SOFT_RESET
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#define MACH_SR_DIAG_CH MIPS_4K_SR_DIAG_CH
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#define MACH_SR_DIAG_CE MIPS_4K_SR_DIAG_CE
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#define MACH_SR_DIAG_PE MIPS_4K_SR_DIAG_PE
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#define MACH_SR_KX MIPS_4K_SR_KX
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#define MACH_SR_SX MIPS_4K_SR_SX
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#define MACH_SR_UX MIPS_4K_SR_UX
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#define MACH_SR_KSU_MASK MIPS_4K_SR_KSU_MASK
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#define MACH_SR_KSU_USER MIPS_4K_SR_KSU_USER
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#define MACH_SR_KSU_SUPER MIPS_4K_SR_KSU_SUPER
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#define MACH_SR_KSU_KERNEL MIPS_4K_SR_KSU_KERNEL
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#define MACH_SR_ERL MIPS_4K_SR_ERL
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#define MACH_SR_EXL MIPS_4K_SR_EXL
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/*
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* The interrupt masks.
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* If a bit in the mask is 1 then the interrupt is enabled (or pending).
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*/
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#define MIPS_INT_MASK 0xff00
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#define MACH_INT_MASK_5 0x8000
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#define MACH_INT_MASK_4 0x4000
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#define MACH_INT_MASK_3 0x2000
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#define MACH_INT_MASK_2 0x1000
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#define MACH_INT_MASK_1 0x0800
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#define MACH_INT_MASK_0 0x0400
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#define MIPS_HARD_INT_MASK 0xfc00
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#define MACH_SOFT_INT_MASK_1 0x0200
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#define MACH_SOFT_INT_MASK_0 0x0100
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#ifdef pmax
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#define MACH_INT_MASK MIPS_INT_MASK
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#define MACH_HARD_INT_MASK MIPS_HARD_INT_MASK
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#endif
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/* r4000 has on-chip timer at INT_MASK_5 */
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#ifdef pica
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#define MACH_INT_MASK (MIPS_INT_MASK & ~MACH_INT_MASK_5)
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#define MACH_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MACH_INT_MASK_5)
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#endif
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/*
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* The bits in the context register.
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*/
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#define MIPS_3K_CNTXT_PTE_BASE 0xFFE00000
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#define MIPS_3K_CNTXT_BAD_VPN 0x001FFFFC
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#define MIPS_4K_CNTXT_PTE_BASE 0xFF800000
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#define MIPS_4K_CNTXT_BAD_VPN2 0x007FFFF0
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/*
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* Backwards compatbility -- XXX more thought
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*/
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#ifdef pmax
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#define MACH_CNTXT_PTE_BASE MIPS_3K_CNTXT_PTE_BASE
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#define MACH_CNTXT_BAD_VPN MIPS_3K_CNTXT_BAD_VPN
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#endif /* pmax */
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#ifdef pica
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#define MACH_CNTXT_PTE_BASE MIPS_4K_CNTXT_PTE_BASE
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#define MACH_CNTXT_BAD_VPN2 MIPS_4K_CNTXT_BAD_VPN2
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#endif /* pica */
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/*
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* Location of exception vectors.
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*
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* Common vectors: reset and UTLB miss.
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*/
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#define MACH_RESET_EXC_VEC 0xBFC00000
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#define MACH_UTLB_MISS_EXC_VEC 0x80000000
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/*
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* R3000 general exception vector (everything else)
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*/
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#define MIPS_3K_GEN_EXC_VEC 0x80000080
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/*
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* R4000 MIPS-III exception vectors
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*/
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#define MIPS_4K_XTLB_MISS_EXC_VEC 0x80000080
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#define MIPS_4K_CACHE_ERR_EXC_VEC 0x80000100
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#define MIPS_4K_GEN_EXC_VEC 0x80000180
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/*
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* Backwards compatbility -- XXX more thought
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*/
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#ifdef pmax
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#define MACH_GEN_EXC_VEC MIPS_3K_GEN_EXC_VEC
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#endif /* pmax */
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#ifdef pica
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#define MACH_GEN_EXC_VEC MIPS_4K_GEN_EXC_VEC
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#define MACH_TLB_MISS_EXC_VEC MACH_UTLB_MISS_EXC_VEC /* locore compat */
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#define MACH_XTLB_MISS_EXC_VEC MIPS_4K_XTLB_MISS_EXC_VEC
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#define MACH_CACHE_ERR_EXC_VEC MIPS_4K_CACHE_ERR_EXC_VEC
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#endif /* pica */
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/*
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* Coprocessor 0 registers:
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*
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* MACH_COP_0_TLB_INDEX TLB index.
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* MACH_COP_0_TLB_RANDOM TLB random.
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* MACH_COP_0_TLB_LOW r3k TLB entry low.
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* MACH_COP_0_TLB_LO0 r4k TLB entry low.
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* MACH_COP_0_TLB_LO1 r4k TLB entry low, extended.
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* MACH_COP_0_TLB_CONTEXT TLB context.
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* MACH_COP_0_BAD_VADDR Bad virtual address.
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* MACH_COP_0_TLB_HI TLB entry high.
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* MACH_COP_0_STATUS_REG Status register.
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* MACH_COP_0_CAUSE_REG Exception cause register.
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* MACH_COP_0_EXC_PC Exception PC.
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* MACH_COP_0_PRID Processor revision identifier.
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*/
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#define MACH_COP_0_TLB_INDEX $0
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#define MACH_COP_0_TLB_RANDOM $1
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/* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
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#define MACH_COP_0_TLB_CONTEXT $4
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/* $5 and $6 new with MIPS-III */
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#define MACH_COP_0_BAD_VADDR $8
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#define MACH_COP_0_TLB_HI $10
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#define MACH_COP_0_STATUS_REG $12
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#define MACH_COP_0_CAUSE_REG $13
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#define MACH_COP_0_EXC_PC $14
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#define MACH_COP_0_PRID $15
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/* r3k-specific */
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#define MACH_COP_0_TLB_LOW $2
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/* MIPS-III additions */
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#define MACH_COP_0_TLB_LO0 $2
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#define MACH_COP_0_TLB_LO1 $3
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#define MACH_COP_0_TLB_PG_MASK $5
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#define MACH_COP_0_TLB_WIRED $6
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#define MACH_COP_0_CONFIG $16
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#define MACH_COP_0_LLADDR $17
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#define MACH_COP_0_WATCH_LO $18
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#define MACH_COP_0_WATCH_HI $19
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#define MACH_COP_0_TLB_XCONTEXT $20
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#define MACH_COP_0_ECC $26
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#define MACH_COP_0_CACHE_ERR $27
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#define MACH_COP_0_TAG_LO $28
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#define MACH_COP_0_TAG_HI $29
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#define MACH_COP_0_ERROR_PC $30
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/*
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* Values for the code field in a break instruction.
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*/
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#define MACH_BREAK_INSTR 0x0000000d
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#define MACH_BREAK_VAL_MASK 0x03ff0000
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#define MACH_BREAK_VAL_SHIFT 16
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#define MACH_BREAK_KDB_VAL 512
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#define MACH_BREAK_SSTEP_VAL 513
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#define MACH_BREAK_BRKPT_VAL 514
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#define MACH_BREAK_SOVER_VAL 515
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#define MACH_BREAK_KDB (MACH_BREAK_INSTR | \
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(MACH_BREAK_KDB_VAL << MACH_BREAK_VAL_SHIFT))
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#define MACH_BREAK_SSTEP (MACH_BREAK_INSTR | \
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(MACH_BREAK_SSTEP_VAL << MACH_BREAK_VAL_SHIFT))
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#define MACH_BREAK_BRKPT (MACH_BREAK_INSTR | \
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(MACH_BREAK_BRKPT_VAL << MACH_BREAK_VAL_SHIFT))
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#define MACH_BREAK_SOVER (MACH_BREAK_INSTR | \
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(MACH_BREAK_SOVER_VAL << MACH_BREAK_VAL_SHIFT))
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/*
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* Mininum and maximum cache sizes.
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*/
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#define MACH_MIN_CACHE_SIZE (16 * 1024)
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#define MACH_MAX_CACHE_SIZE (256 * 1024)
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/*
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* The floating point version and status registers.
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*/
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#define MACH_FPC_ID $0
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#define MACH_FPC_CSR $31
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/*
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* The floating point coprocessor status register bits.
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*/
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#define MACH_FPC_ROUNDING_BITS 0x00000003
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#define MACH_FPC_ROUND_RN 0x00000000
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#define MACH_FPC_ROUND_RZ 0x00000001
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#define MACH_FPC_ROUND_RP 0x00000002
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#define MACH_FPC_ROUND_RM 0x00000003
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#define MACH_FPC_STICKY_BITS 0x0000007c
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#define MACH_FPC_STICKY_INEXACT 0x00000004
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#define MACH_FPC_STICKY_UNDERFLOW 0x00000008
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#define MACH_FPC_STICKY_OVERFLOW 0x00000010
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#define MACH_FPC_STICKY_DIV0 0x00000020
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#define MACH_FPC_STICKY_INVALID 0x00000040
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#define MACH_FPC_ENABLE_BITS 0x00000f80
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#define MACH_FPC_ENABLE_INEXACT 0x00000080
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#define MACH_FPC_ENABLE_UNDERFLOW 0x00000100
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#define MACH_FPC_ENABLE_OVERFLOW 0x00000200
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#define MACH_FPC_ENABLE_DIV0 0x00000400
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#define MACH_FPC_ENABLE_INVALID 0x00000800
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#define MACH_FPC_EXCEPTION_BITS 0x0003f000
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#define MACH_FPC_EXCEPTION_INEXACT 0x00001000
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#define MACH_FPC_EXCEPTION_UNDERFLOW 0x00002000
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#define MACH_FPC_EXCEPTION_OVERFLOW 0x00004000
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#define MACH_FPC_EXCEPTION_DIV0 0x00008000
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#define MACH_FPC_EXCEPTION_INVALID 0x00010000
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#define MACH_FPC_EXCEPTION_UNIMPL 0x00020000
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#define MACH_FPC_COND_BIT 0x00800000
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#define MACH_FPC_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
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#define MIPS_3K_FPC_MBZ_BITS 0xff7c0000
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#define MIPS_4K_FPC_MBZ_BITS 0xfe7c0000
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/*
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* Constants to determine if have a floating point instruction.
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*/
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#define MACH_OPCODE_SHIFT 26
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#define MACH_OPCODE_C1 0x11
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/*
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* The low part of the TLB entry.
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*/
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#define VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT 12
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#define VMMACH_MIPS_3K_TLB_PF_NUM 0xfffff000
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#define VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT 0x00000800
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#define VMMACH_MIPS_3K_TLB_MOD_BIT 0x00000400
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#define VMMACH_MIPS_3K_TLB_VALID_BIT 0x00000200
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#define VMMACH_MIPS_3K_TLB_GLOBAL_BIT 0x00000100
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#define VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT 6
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#define VMMACH_MIPS_4K_TLB_PF_NUM 0x3fffffc0
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#define VMMACH_MIPS_4K_TLB_ATTR_MASK 0x00000038
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#define VMMACH_MIPS_4K_TLB_MOD_BIT 0x00000004
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#define VMMACH_MIPS_4K_TLB_VALID_BIT 0x00000002
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#define VMMACH_MIPS_4K_TLB_GLOBAL_BIT 0x00000001
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#ifdef pmax /* XXX */
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#define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_3K_TLB_PHYS_PAGE_SHIFT
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#define VMMACH_TLB_PF_NUM VMMACH_MIPS_3K_TLB_PF_NUM
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#define VMMACH_TLB_NON_CACHEABLE_BIT VMMACH_MIPS_3K_TLB_NON_CACHEABLE_BIT
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#define VMMACH_TLB_MOD_BIT VMMACH_MIPS_3K_TLB_MOD_BIT
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#define VMMACH_TLB_VALID_BIT VMMACH_MIPS_3K_TLB_VALID_BIT
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#define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_3K_TLB_GLOBAL_BIT
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#endif /* pmax */
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#ifdef pica /* XXX */
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#define VMMACH_TLB_PHYS_PAGE_SHIFT VMMACH_MIPS_4K_TLB_PHYS_PAGE_SHIFT
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#define VMMACH_TLB_PF_NUM VMMACH_MIPS_4K_TLB_PF_NUM
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#define VMMACH_TLB_ATTR_MASK VMMACH_MIPS_4K_TLB_ATTR_MASK
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#define VMMACH_TLB_MOD_BIT VMMACH_MIPS_4K_TLB_MOD_BIT
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#define VMMACH_TLB_VALID_BIT VMMACH_MIPS_4K_TLB_VALID_BIT
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#define VMMACH_TLB_GLOBAL_BIT VMMACH_MIPS_4K_TLB_GLOBAL_BIT
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#endif /* pica */
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/*
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* The high part of the TLB entry.
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*/
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#define VMMACH_TLB_VIRT_PAGE_SHIFT 12
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#define VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM 0xfffff000
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#define VMMACH_TLB_MIPS_3K_PID 0x00000fc0
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#define VMMACH_TLB_MIPS_3K_PID_SHIFT 6
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#define VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM 0xffffe000
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#define VMMACH_TLB_MIPS_4K_PID 0x000000ff
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#define VMMACH_TLB_MIPS_4K_PID_SHIFT 0
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/* XXX needs more thought */
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/*
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* backwards XXX needs more thought, should support runtime decisions.
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*/
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#ifdef pmax
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#define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_3K_VIRT_PAGE_NUM
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#define VMMACH_TLB_PID VMMACH_TLB_MIPS_3K_PID
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#define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_3K_PID_SHIFT
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#endif
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#ifdef pica
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#define VMMACH_TLB_VIRT_PAGE_NUM VMMACH_TLB_MIPS_4K_VIRT_PAGE_NUM
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#define VMMACH_TLB_PID VMMACH_TLB_MIPS_4K_PID
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#define VMMACH_TLB_PID_SHIFT VMMACH_TLB_MIPS_4K_PID_SHIFT
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#endif
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/*
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* r3000: shift count to put the index in the right spot.
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* (zero on r4000?)
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*/
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#define VMMACH_TLB_INDEX_SHIFT 8
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/*
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* The number of TLB entries and the first one that write random hits.
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*/
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#define VMMACH_MIPS_3K_NUM_TLB_ENTRIES 64
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#define VMMACH_MIPS_3K_FIRST_RAND_ENTRY 8
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#define VMMACH_MIPS_4K_NUM_TLB_ENTRIES 48
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#define VMMACH_MIPS_4K_WIRED_ENTRIES 8
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/* compatibility with existing locore -- XXX more thought */
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#ifdef pmax
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#define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_3K_NUM_TLB_ENTRIES
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#define VMMACH_FIRST_RAND_ENTRY VMMACH_MIPS_3K_FIRST_RAND_ENTRY
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#endif /* pmax */
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#ifdef pica
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#define VMMACH_NUM_TLB_ENTRIES VMMACH_MIPS_4K_NUM_TLB_ENTRIES
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#define VMMACH_WIRED_ENTRIES VMMACH_MIPS_4K_WIRED_ENTRIES
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#endif /* pica */
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/*
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* The number of process id entries.
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*/
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#define VMMACH_MIPS_3K_NUM_PIDS 64
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#define VMMACH_MIPS_4K_NUM_PIDS 256
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#ifdef pmax
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#define VMMACH_NUM_PIDS VMMACH_MIPS_3K_NUM_PIDS
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#endif /* pmax */
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#ifdef pica
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#define VMMACH_NUM_PIDS VMMACH_MIPS_4K_NUM_PIDS
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#endif /* pica */
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/*
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* TLB probe return codes.
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*/
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#define VMMACH_TLB_NOT_FOUND 0
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#define VMMACH_TLB_FOUND 1
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#define VMMACH_TLB_FOUND_WITH_PATCH 2
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#define VMMACH_TLB_PROBE_ERROR 3
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#endif /* _MACHCONST */
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