rumble 9b1a76ecf8 The wd33c93 chip appears to be clocked at 20MHz for all systems with a HPC.		2007-03-30 19:04:40 +00:00
..
dp8573areg.h	…
dpclock_hpc.c	…
dsclock_hpc.c	…
files.hpc	…
haltwo.c	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
haltworeg.h	…
haltwovar.h	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
hpc.c	Make this compile again.	2007-02-22 01:04:18 +00:00
hpcdma.c	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
hpcdma.h	…
hpcreg.h	Support the sq(4) interface on the Challenge S's IOPLUS mezzanine. This	2007-02-19 20:14:30 +00:00
hpcvar.h	Prefix 'dma_data{in,out}_cmd' with 'scsi_', since that's what they're used	2006-12-22 23:36:42 +00:00
if_sq.c	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
pckbc_hpc.c	…
pi1ppc.c	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
pi1ppcreg.h	…
pi1ppcvar.h	Kill caddr_t; there will be some MI fallout, but it will be fixed shortly.	2007-03-04 05:59:00 +00:00
sqvar.h	…
wdsc.c	The wd33c93 chip appears to be clocked at 20MHz for all systems with a HPC.	2007-03-30 19:04:40 +00:00