339 lines
9.3 KiB
C
339 lines
9.3 KiB
C
/* $NetBSD: ifpga.c,v 1.21 2005/12/11 12:17:09 christos Exp $ */
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/*
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* Copyright (c) 2001 ARM Ltd
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the company may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Integrator FPGA core logic support.
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*
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* The integrator board supports the core logic in an FPGA which is loaded
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* at POR with a custom design. This code supports the default logic as the
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* board is shipped.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: ifpga.c,v 1.21 2005/12/11 12:17:09 christos Exp $");
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#include <sys/types.h>
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#include <sys/device.h>
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#include <sys/systm.h>
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#include <sys/extent.h>
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#include <sys/malloc.h>
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#include <sys/null.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pciconf.h>
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#include <machine/intr.h>
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#include <arm/cpufunc.h>
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#include "opt_pci.h"
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#include "pci.h"
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#include <evbarm/ifpga/ifpgamem.h>
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#include <evbarm/ifpga/ifpgavar.h>
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#include <evbarm/ifpga/ifpgareg.h>
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#include <evbarm/ifpga/ifpga_pcivar.h>
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#include <evbarm/dev/v360reg.h>
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#include <evbarm/integrator/int_bus_dma.h>
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#include "locators.h"
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/* Prototypes */
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static int ifpga_match (struct device *, struct cfdata *, void *);
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static void ifpga_attach (struct device *, struct device *, void *);
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static int ifpga_print (void *, const char *);
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/* Drive and attach structures */
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CFATTACH_DECL(ifpga, sizeof(struct ifpga_softc),
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ifpga_match, ifpga_attach, NULL, NULL);
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int ifpga_found;
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/* Default UART clock speed (we should make this a boot option). */
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int ifpga_uart_clk = IFPGA_UART_CLK;
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#if NPCI > 0
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/* PCI handles */
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extern struct arm32_pci_chipset ifpga_pci_chipset;
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extern struct arm32_bus_dma_tag ifpga_pci_bus_dma_tag;
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static struct bus_space ifpga_pci_io_tag;
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static struct bus_space ifpga_pci_mem_tag;
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#endif /* NPCI > 0 */
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static struct bus_space ifpga_bs_tag;
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struct ifpga_softc *ifpga_sc;
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/*
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* Print the configuration information for children
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*/
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static int
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ifpga_print(void *aux, const char *pnp)
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{
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struct ifpga_attach_args *ifa = aux;
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if (ifa->ifa_addr != -1)
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aprint_normal(" addr 0x%lx", (unsigned long)ifa->ifa_addr);
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if (ifa->ifa_irq != -1)
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aprint_normal(" irq %d", ifa->ifa_irq);
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return UNCONF;
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}
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static int
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ifpga_search(struct device *parent, struct cfdata *cf,
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const int *ldesc, void *aux)
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{
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struct ifpga_softc *sc = (struct ifpga_softc *)parent;
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struct ifpga_attach_args ifa;
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int tryagain;
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do {
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ifa.ifa_iot = sc->sc_iot;
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ifa.ifa_addr = cf->cf_iobase;
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ifa.ifa_irq = cf->cf_irq;
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ifa.ifa_sc_ioh = sc->sc_sc_ioh;
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tryagain = 0;
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if (config_match(parent, cf, &ifa) > 0) {
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config_attach(parent, cf, &ifa, ifpga_print);
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tryagain = (cf->cf_fstate == FSTATE_STAR);
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}
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} while (tryagain);
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return 0;
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}
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static int
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ifpga_match(struct device *parent, struct cfdata *cf, void *aux)
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{
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#if 0
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struct mainbus_attach_args *ma = aux;
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/* Make sure that we're looking for the IFPGA. */
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if (strcmp(ma->ma_name, ifpga_md.md_name))
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return 0;
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#endif
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/* We can only have one instance of the IFPGA. */
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if (ifpga_found)
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return 0;
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return 1;
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}
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static void
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ifpga_attach(struct device *parent, struct device *self, void *aux)
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{
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struct ifpga_softc *sc = (struct ifpga_softc *)self;
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u_int id, sysclk;
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#if defined(PCI_NETBSD_CONFIGURE) && NPCI > 0
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struct extent *ioext, *memext, *pmemext;
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struct ifpga_pci_softc *pci_sc;
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struct pcibus_attach_args pci_pba;
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#endif
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ifpga_found = 1;
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/* We want a memory-mapped bus space, since the I/O space is sparse. */
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ifpga_create_mem_bs_tag(&ifpga_bs_tag, (void *)IFPGA_IO_BASE);
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#if NPCI > 0
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/* But the PCI config space is quite large, so we have a linear region
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for that pre-allocated. */
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ifpga_create_io_bs_tag(&ifpga_pci_io_tag, (void *)IFPGA_PCI_IO_VBASE);
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ifpga_create_mem_bs_tag(&ifpga_pci_mem_tag, (void *)0);
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#endif
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sc->sc_iot = &ifpga_bs_tag;
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ifpga_sc = sc;
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/* Now map in the IFPGA motherboard registers. */
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if (bus_space_map(sc->sc_iot, IFPGA_IO_SC_BASE, IFPGA_IO_SC_SIZE, 0,
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&sc->sc_sc_ioh))
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panic("%s: Cannot map system controller registers",
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self->dv_xname);
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id = bus_space_read_4(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_ID);
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printf(": Build %d, ", (id & IFPGA_SC_ID_BUILD_MASK) >>
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IFPGA_SC_ID_BUILD_SHIFT);
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switch (id & IFPGA_SC_ID_REV_MASK)
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{
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case IFPGA_SC_ID_REV_A:
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printf("Rev A, ");
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break;
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case IFPGA_SC_ID_REV_B:
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printf("Rev B, ");
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break;
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}
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printf("Manufacturer ");
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switch (id & IFPGA_SC_ID_MAN_MASK)
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{
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case IFPGA_SC_ID_MAN_ARM:
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printf("ARM Ltd,");
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break;
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default:
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printf("Unknown,");
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break;
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}
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switch (id & IFPGA_SC_ID_ARCH_MASK)
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{
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case IFPGA_SC_ID_ARCH_ASBLE:
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printf(" ASB, Little-endian,");
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break;
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case IFPGA_SC_ID_ARCH_AHBLE:
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printf(" AHB, Little-endian,");
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break;
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default:
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panic(" Unsupported bus");
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}
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printf("\n%s: FPGA ", self->dv_xname);
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switch (id & IFPGA_SC_ID_FPGA_MASK)
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{
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case IFPGA_SC_ID_FPGA_XC4062:
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printf("XC4062");
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break;
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case IFPGA_SC_ID_FPGA_XC4085:
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printf("XC4085");
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break;
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default:
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printf("unknown");
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break;
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}
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sysclk = bus_space_read_1(sc->sc_iot, sc->sc_sc_ioh, IFPGA_SC_OSC);
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sysclk &= IFPGA_SC_OSC_S_VDW;
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sysclk += 8;
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printf(", SYSCLK %d.%02dMHz", sysclk >> 2, (sysclk & 3) * 25);
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/* Map the Interrupt controller */
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if (bus_space_map(sc->sc_iot, IFPGA_IO_IRQ_BASE, IFPGA_IO_IRQ_SIZE,
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BUS_SPACE_MAP_LINEAR, &sc->sc_irq_ioh))
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panic("%s: Cannot map irq controller registers",
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self->dv_xname);
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/* We can write to the IRQ/FIQ controller now. */
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ifpga_intr_postinit();
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/* Map the core module */
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if (bus_space_map(sc->sc_iot, IFPGA_IO_CM_BASE, IFPGA_IO_CM_SIZE, 0,
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&sc->sc_cm_ioh))
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panic("%s: Cannot map core module registers", self->dv_xname);
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/* Map the timers */
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if (bus_space_map(sc->sc_iot, IFPGA_IO_TMR_BASE, IFPGA_IO_TMR_SIZE, 0,
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&sc->sc_tmr_ioh))
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panic("%s: Cannot map timer registers", self->dv_xname);
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printf("\n");
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#if NPCI > 0
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pci_sc = malloc(sizeof(struct ifpga_pci_softc), M_DEVBUF, M_WAITOK);
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pci_sc->sc_iot = &ifpga_pci_io_tag;
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pci_sc->sc_memt = &ifpga_pci_mem_tag;
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if (bus_space_map(pci_sc->sc_iot, 0, IFPGA_PCI_IO_VSIZE, 0,
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&pci_sc->sc_io_ioh)
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|| bus_space_map(pci_sc->sc_iot,
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IFPGA_PCI_CONF_VBASE - IFPGA_PCI_IO_VBASE, IFPGA_PCI_CONF_VSIZE, 0,
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&pci_sc->sc_conf_ioh)
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|| bus_space_map(pci_sc->sc_memt, IFPGA_V360_REG_BASE,
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IFPGA_V360_REG_SIZE, 0, &pci_sc->sc_reg_ioh))
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panic("%s: Cannot map pci memory", self->dv_xname);
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{
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pcireg_t id_reg, class_reg;
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char buf[1000];
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id_reg = bus_space_read_4(pci_sc->sc_memt, pci_sc->sc_reg_ioh,
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V360_PCI_VENDOR);
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class_reg = bus_space_read_4(pci_sc->sc_memt,
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pci_sc->sc_reg_ioh, V360_PCI_CC_REV);
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pci_devinfo(id_reg, class_reg, 1, buf, sizeof(buf));
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printf("%s: %s\n", self->dv_xname, buf);
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}
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#if defined(PCI_NETBSD_CONFIGURE)
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ioext = extent_create("pciio", 0x00000000,
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0x00000000 + IFPGA_PCI_IO_VSIZE, M_DEVBUF, NULL, 0, EX_NOWAIT);
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memext = extent_create("pcimem", IFPGA_PCI_APP0_BASE,
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IFPGA_PCI_APP0_BASE + IFPGA_PCI_APP0_SIZE,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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pmemext = extent_create("pcipmem", IFPGA_PCI_APP1_BASE,
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IFPGA_PCI_APP1_BASE + IFPGA_PCI_APP1_SIZE,
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M_DEVBUF, NULL, 0, EX_NOWAIT);
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ifpga_pci_chipset.pc_conf_v = (void *)pci_sc;
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pci_configure_bus(&ifpga_pci_chipset, ioext, memext, pmemext, 0,
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arm_dcache_align);
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extent_destroy(pmemext);
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extent_destroy(memext);
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extent_destroy(ioext);
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printf("pci_configure_bus done\n");
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#endif /* PCI_NETBSD_CONFIGURE */
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#endif /* NPCI > 0 */
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/* Finally, search for children. */
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config_search_ia(ifpga_search, self, "ifpga", NULL);
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#if NPCI > 0
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integrator_pci_dma_init(&ifpga_pci_bus_dma_tag);
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pci_pba.pba_pc = &ifpga_pci_chipset;
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pci_pba.pba_iot = &ifpga_pci_io_tag;
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pci_pba.pba_memt = &ifpga_pci_mem_tag;
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pci_pba.pba_dmat = &ifpga_pci_bus_dma_tag;
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pci_pba.pba_dmat64 = NULL;
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pci_pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED;
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pci_pba.pba_bus = 0;
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pci_pba.pba_bridgetag = NULL;
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config_found_ia(self, "pcibus", &pci_pba, pcibusprint);
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#endif
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}
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void
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ifpga_reset(void)
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{
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bus_space_write_1(ifpga_sc->sc_iot, ifpga_sc->sc_sc_ioh,
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IFPGA_SC_CTRLS, IFPGA_SC_CTRL_SOFTRESET);
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}
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