discover it, but make it block on a semaphore until the MI kernel
says that we can let the secondary processors loose. This allows
us to announce the extensions on the secondary CPUs, and to compute
the intersection of all the extensions across all CPUs, like so:
cpu0 at mainbus0: ID 0 (primary), 21164A-2
cpu0: Architecture extensions: 1<BWX>
cpu1 at mainbus0: ID 1, 21164A-2
cpu1: Architecture extensions: 1<BWX>
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