473 lines
19 KiB
C
473 lines
19 KiB
C
/* $NetBSD: icureg.h,v 1.7 2002/02/11 11:44:36 takemura Exp $ */
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/*-
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* Copyright (c) 1999 Shin Takemura. All rights reserved.
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* Copyright (c) 1999-2001 SATO Kazumi. All rights reserved.
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* Copyright (c) 1999 PocketBSD Project. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the PocketBSD project
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* and its contributors.
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* 4. Neither the name of the project nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/*
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* ICU (Interrupt Control UNIT) Registers definitions
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* start 0x0B000080 (vr4102/4111/4121)
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* start 0x0F000080 (vr4122)
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*/
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#include "opt_vr41xx.h"
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#include <hpcmips/vr/vrcpudef.h>
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#define ICU_NO_REG_W 0xffffffff /* no register */
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/* SYSINT1 & MSYSINT1 */
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#define SYSINT1_REG_W 0x000 /* Level1 System intr reg 1 */
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#define MSYSINT1_REG_W 0x00c /* Level1 Mask System intr reg 1 */
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#define SYSINT1_INT15 (1<<15)
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#define SYSINT1_INT14 (1<<14)
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#define SYSINT1_INT13 (1<<13)
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#define SYSINT1_DOZEPIU (1<<13) /* PIU intr during Suspend */
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#define SYSINT1_INT12 (1<<12)
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#define SYSINT1_CLKRUN (1<<12) /* CLKRUN intr (=vr4122) */
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#define SYSINT1_INT11 (1<<11)
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#define SYSINT1_SOFT (1<<11) /* Software intr */
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#define SYSINT1_INT10 (1<<10)
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#define SYSINT1_WRBERR (1<<10) /* Bus error intr (4102 <=,<= 4121)*/
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#define SYSINT1_INT9 (1<<9)
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#define SYSINT1_SIU (1<<9) /* SIU intr */
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#define SYSINT1_INT8 (1<<8)
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#define SYSINT1_GIU (1<<8) /* GIU intr */
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#define SYSINT1_INT7 (1<<7)
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#define SYSINT1_KIU (1<<7) /* KIU intr (4102 <=,<= 4121)*/
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#define SYSINT1_INT6 (1<<6)
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#define SYSINT1_AIU (1<<6) /* AIU intr (4102 <=,<= 4121)*/
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#define SYSINT1_INT5 (1<<5)
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#define SYSINT1_PIU (1<<5) /* PIU intr (4102 <=,<= 4121)*/
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#define SYSINT1_INT4 (1<<4)
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#define SYSINT1_INT3 (1<<3)
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#define SYSINT1_ETIMER (1<<3) /* ETIMER intr */
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#define SYSINT1_INT2 (1<<2)
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#define SYSINT1_RTCL1 (1<<2) /* RTClong1 intr */
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#define SYSINT1_INT1 (1<<1)
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#define SYSINT1_POWER (1<<1) /* PowerSW intr */
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#define SYSINT1_INT0 (1<<0)
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#define SYSINT1_BAT (1<<0) /* Battery intr */
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/* PIUINT & MPIUINT */
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#define ICUPIUINT_REG_W 0x002 /* Level2 PIU intr reg */
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#define MPIUINT_REG_W 0x00e /* Level2 Mask PIU intr reg */
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#define PIUINT_PADCMD (1<<6) /* PIU command scan intr */
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#define PIUINT_PADADP (1<<5) /* PIU AD port scan intr */
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#define PIUINT_PADPAGE1 (1<<4) /* PIU data page 1 intr */
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#define PIUINT_PADPAGE0 (1<<3) /* PIU data page 0 intr */
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#define PIUINT_PADLOST (1<<2) /* A/D data timeout intr */
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#define PIUINT_PENCHG (1) /* Touch Panel contact intr */
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/* AIUINT & MAIUINT */
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#define VR4102_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
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#define VR4102_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
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#define VR4122_AIUINT_REG_W ICU_NO_REG_W /* Level2 AIU intr reg */
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#define VR4122_MAIUINT_REG_W ICU_NO_REG_W /* Level2 Mask AIU intr reg */
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#define VR4181_AIUINT_REG_W 0x004 /* Level2 AIU intr reg */
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#define VR4181_MAIUINT_REG_W 0x010 /* Level2 Mask AIU intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define AIUINT_REG_W VR4102_AIUINT_REG_W
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#define MAIUINT_REG_W VR4102_MAIUINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define AIUINT_REG_W VR4122_AIUINT_REG_W
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#define MAIUINT_REG_W VR4122_MAIUINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define AIUINT_REG_W VR4181_AIUINT_REG_W
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#define MAIUINT_REG_W VR4181_MAIUINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define AIUINT_INTMEND (1<<11) /* Audio input DMA buffer 2 page */
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#define AIUINT_INTM (1<<10) /* Audio input DMA buffer 1 page */
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#define AIUINT_INTMIDLE (1<<9) /* Audio input idle intr */
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#define AIUINT_INTMST (1<<8) /* Audio input receive completion intr */
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#define AIUINT_INTSEND (1<<3) /* Audio output buffer 2 page */
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#define AIUINT_INTS (1<<2) /* Audio output buffer 1 page */
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#define AIUINT_INTSIDLE (1<<1) /* Audio output idle intr */
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/* KIUINT & MKIUINT */
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#define VR4102_KIUINT_REG_W 0x006 /* Level2 KIU intr reg */
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#define VR4102_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
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#define VR4122_KIUINT_REG_W ICU_NO_REG_W /* Level2 KIU intr reg */
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#define VR4122_MKIUINT_REG_W ICU_NO_REG_W /* Level2 Mask KIU intr reg */
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#define VR4181_KIUINT_REG_W 0x118 /* Level2 KIU intr reg */
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#define VR4181_MKIUINT_REG_W 0x012 /* Level2 Mask KIU intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define KIUINT_REG_W VR4102_KIUINT_REG_W
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#define MKIUINT_REG_W VR4102_MKIUINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define KIUINT_REG_W VR4122_KIUINT_REG_W
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#define MKIUINT_REG_W VR4122_MKIUINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define KIUINT_REG_W VR4181_KIUINT_REG_W
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#define MKIUINT_REG_W VR4181_MKIUINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define KIUINT_KDATLOST (1<<2) /* Key scan data lost */
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#define KIUINT_KDATRDY (1<<1) /* Key scan data complete */
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#define KIUINT_SCANINT (1) /* Key input detect intr */
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/* GIUINTL & MGIUINTL */
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#define VR4102_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
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#define VR4102_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
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#define VR4122_GIUINT_L_REG_W 0x008 /* Level2 GIU intr reg Low */
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#define VR4122_MGIUINT_L_REG_W 0x014 /* Level2 Mask GIU intr reg Low */
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#define VR4181_GIUINT_L_REG_W ICU_NO_REG_W /* Level2 GIU intr reg Low */
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#define VR4181_MGIUINT_L_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg Low */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define GIUINT_L_REG_W VR4102_GIUINT_L_REG_W
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#define MGIUINT_L_REG_W VR4102_MGIUINT_L_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define GIUINT_L_REG_W VR4122_GIUINT_L_REG_W
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#define MGIUINT_L_REG_W VR4122_MGIUINT_L_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define GIUINT_L_REG_W VR4181_GIUINT_L_REG_W
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#define MGIUINT_L_REG_W VR4181_MGIUINT_L_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define GIUINT_GPIO15 (1<<15) /* GPIO 15 */
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#define GIUINT_GPIO14 (1<<14) /* GPIO 14 */
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#define GIUINT_GPIO13 (1<<13) /* GPIO 13 */
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#define GIUINT_GPIO12 (1<<12) /* GPIO 12 */
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#define GIUINT_GPIO11 (1<<11) /* GPIO 11 */
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#define GIUINT_GPIO10 (1<<10) /* GPIO 10 */
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#define GIUINT_GPIO9 (1<<9) /* GPIO 9 */
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#define GIUINT_GPIO8 (1<<8) /* GPIO 8 */
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#define GIUINT_GPIO7 (1<<7) /* GPIO 7 */
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#define GIUINT_GPIO6 (1<<6) /* GPIO 6 */
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#define GIUINT_GPIO5 (1<<5) /* GPIO 5 */
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#define GIUINT_GPIO4 (1<<4) /* GPIO 4 */
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#define GIUINT_GPIO3 (1<<3) /* GPIO 3 */
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#define GIUINT_GPIO2 (1<<2) /* GPIO 2 */
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#define GIUINT_GPIO1 (1<<1) /* GPIO 1 */
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#define GIUINT_GPIO0 (1) /* GPIO 0 */
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/* DSIUINT & MDSIUINT */
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#define VR4102_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
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#define VR4102_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
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#define VR4122_DSIUINT_REG_W 0x00a /* Level2 DSIU intr reg */
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#define VR4122_MDSIUINT_REG_W 0x016 /* Level2 Mask DSIU intr reg */
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#define VR4181_DSIUINT_REG_W ICU_NO_REG_W /* Level2 DSIU intr reg */
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#define VR4181_MDSIUINT_REG_W ICU_NO_REG_W /* Level2 Mask DSIU intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define DSIUINT_REG_W VR4102_DSIUINT_REG_W
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#define MDSIUINT_REG_W VR4102_MDSIUINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define DSIUINT_REG_W VR4122_DSIUINT_REG_W
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#define MDSIUINT_REG_W VR4122_MDSIUINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define DSIUINT_REG_W VR4181_DSIUINT_REG_W
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#define MDSIUINT_REG_W VR4181_MDSIUINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define DSIUINT_DCTS (1<<11) /* DCTS# change */
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#define DSIUINT_SER0 (1<<10) /* Debug serial receive error */
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#define DSIUINT_SR0 (1<<9) /* Debug serial receive */
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#define DSIUINT_ST0 (1<<8) /* Debug serial transmit */
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/* NMI */
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#define NMI_REG_W 0x018 /* NMI reg */
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#define LOWBATT_NMIORINT (1) /* Low battery type */
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#define LOWBATT_INT0 (1) /* Low battery int 0 */
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#define LOWBATT_NMI (0) /* Low battery NMI */
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/* SOFTINT */
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#define SOFTINT_REG_W 0x01a /* Software intr reg */
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#define SOFTINT_MASK3 (1<<3) /* Softint3 mask */
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#define SOFTINT_SET3 (1<<3) /* Softint3 set */
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#define SOFTINT_CLEAR3 (0<<3) /* Softint3 clear */
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#define SOFTINT_MASK2 (1<<2) /* Softint2 mask */
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#define SOFTINT_SET2 (1<<2) /* Softint2 set */
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#define SOFTINT_CLEAR2 (0<<2) /* Softint2 clear */
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#define SOFTINT_MASK1 (1<<1) /* Softint1 mask */
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#define SOFTINT_SET1 (1<<1) /* Softint1 set */
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#define SOFTINT_CLEAR1 (0<<1) /* Softint1 clear */
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#define SOFTINT_MASK0 (1) /* Softint0 mask */
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#define SOFTINT_SET0 (1) /* Softint0 set */
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#define SOFTINT_CLEAR0 (0) /* Softint0 clear */
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/* SYSINT2 & MSYSINT2 */
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#define VR4102_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
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#define VR4102_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */
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#define VR4122_SYSINT2_REG_W 0x020 /* Level1 System intr reg 2 */
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#define VR4122_MSYSINT2_REG_W 0x026 /* Level1 Mask System intr reg 2 */
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#define VR4181_SYSINT2_REG_W 0x180 /* Level1 System intr reg 2 */
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#define VR4181_MSYSINT2_REG_W 0x186 /* Level1 Mask System intr reg 2 */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define SYSINT2_REG_W VR4102_SYSINT2_REG_W
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#define MSYSINT2_REG_W VR4102_MSYSINT2_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define SYSINT2_REG_W VR4122_SYSINT2_REG_W
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#define MSYSINT2_REG_W VR4122_MSYSINT2_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define SYSINT2_REG_W VR4181_SYSINT2_REG_W
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#define MSYSINT2_REG_W VR4181_MSYSINT2_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define SYSINT2_INT31 (1<<15)
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#define SYSINT2_INT30 (1<<14)
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#define SYSINT2_INT29 (1<<13)
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#define SYSINT2_INT28 (1<<12)
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#define SYSINT2_INT27 (1<<11)
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#define SYSINT2_INT26 (1<<10)
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#define SYSINT2_INT25 (1<<9)
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#define SYSINT2_BCU (1<<9) /* BCU intr (=vr4122) */
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#define SYSINT2_INT24 (1<<8)
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#define SYSINT2_CSI (1<<8) /* CSI intr (=vr4122) */
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#define SYSINT2_INT23 (1<<7)
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#define SYSINT2_SCU (1<<7) /* SCU intr (=vr4122) */
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#define SYSINT2_INT22 (1<<6)
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#define SYSINT2_PCI (1<<6) /* PCI intr (=vr4122) */
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#define SYSINT2_LCD (1<<6) /* LCD intr (=vr4181) */
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#define SYSINT2_DSIU (1<<5) /* DSUI intr */
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#define SYSINT2_DCU81 (1<<5) /* DCU intr (=4181) */
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#define SYSINT2_FIR (1<<4) /* FIR intr */
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#define SYSINT2_TCLK (1<<3) /* TClock Counter intr */
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#define SYSINT2_CSI81 (1<<3) /* CSI intr (=4181) */
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#define SYSINT2_HSP (1<<2) /* HSP intr (4122>=4102)*/
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#define SYSINT2_ECU (1<<2) /* EUC intr (=4181)*/
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#define SYSINT2_LED (1<<1) /* LED intr */
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#define SYSINT2_RTCL2 (1<<0) /* RTCLong2 intr */
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/* GIUINTH & MGIUINTH */
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#define VR4102_GIUINT_H_REG_W 0x182 /* Level2 GIU intr reg High */
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#define VR4102_MGIUINT_H_REG_W 0x188 /* Level2 Mask GIU intr reg High */
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#define VR4122_GIUINT_H_REG_W 0x022 /* Level2 GIU intr reg High */
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#define VR4122_MGIUINT_H_REG_W 0x028 /* Level2 Mask GIU intr reg High */
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#define VR4181_GIUINT_H_REG_W ICU_NO_REG_W /* Level2 GIU intr reg High */
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#define VR4181_MGIUINT_H_REG_W ICU_NO_REG_W /* Level2 Mask GIU intr reg High */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define GIUINT_H_REG_W VR4102_GIUINT_H_REG_W
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#define MGIUINT_H_REG_W VR4102_MGIUINT_H_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define GIUINT_H_REG_W VR4122_GIUINT_H_REG_W
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#define MGIUINT_H_REG_W VR4122_MGIUINT_H_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define GIUINT_H_REG_W VR4181_GIUINT_H_REG_W
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#define MGIUINT_H_REG_W VR4181_MGIUINT_H_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define GIUINT_GPIO31 (1<<15) /* GPIO 31 */
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#define GIUINT_GPIO30 (1<<14) /* GPIO 30 */
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#define GIUINT_GPIO29 (1<<13) /* GPIO 29 */
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#define GIUINT_GPIO28 (1<<12) /* GPIO 28 */
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#define GIUINT_GPIO27 (1<<11) /* GPIO 27 */
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#define GIUINT_GPIO26 (1<<10) /* GPIO 26 */
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#define GIUINT_GPIO25 (1<<9) /* GPIO 25 */
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#define GIUINT_GPIO24 (1<<8) /* GPIO 24 */
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#define GIUINT_GPIO23 (1<<7) /* GPIO 23 */
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#define GIUINT_GPIO22 (1<<6) /* GPIO 22 */
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#define GIUINT_GPIO21 (1<<5) /* GPIO 21 */
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#define GIUINT_GPIO20 (1<<4) /* GPIO 20 */
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#define GIUINT_GPIO19 (1<<3) /* GPIO 19 */
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#define GIUINT_GPIO18 (1<<2) /* GPIO 18 */
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#define GIUINT_GPIO17 (1<<1) /* GPIO 17 */
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#define GIUINT_GPIO16 (1) /* GPIO 16 */
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/* FIRINT & MFIRINT */
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#define VR4102_FIRINT_REG_W 0x184 /* Level2 FIR intr reg */
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#define VR4102_MFIRINT_REG_W 0x18a /* Level2 Mask FIR intr reg */
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#define VR4122_FIRINT_REG_W 0x024 /* Level2 FIR intr reg */
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#define VR4122_MFIRINT_REG_W 0x02a /* Level2 Mask FIR intr reg */
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#define VR4181_FIRINT_REG_W ICU_NO_REG_W /* Level2 FIR intr reg */
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#define VR4181_MFIRINT_REG_W ICU_NO_REG_W /* Level2 Mask FIR intr reg */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define FIRINT_REG_W VR4102_FIRINT_REG_W
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#define MFIRINT_REG_W VR4102_MFIRINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define FIRINT_REG_W VR4122_FIRINT_REG_W
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#define MFIRINT_REG_W VR4122_MFIRINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define FIRINT_REG_W VR4181_FIRINT_REG_W
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#define MFIRINT_REG_W VR4181_MFIRINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define FIRINT_FIR (1<<4) /* FIR intr */
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#define FIRINT_RECV2 (1<<3) /* FIR DMA buf recv buffer2 */
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#define FIRINT_TRNS2 (1<<2) /* FIR DMA buf transmit buffer2 */
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#define FIRINT_RECV1 (1<<1) /* FIR DMA buf recv buffer1 */
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#define FIRINT_TRNS1 (1) /* FIR DMA buf transmit buffer1 */
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/* PCIINT & MPCIINT */
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#define VR4102_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
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#define VR4102_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
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#define VR4122_PCIINT_REG_W 0x2c /* Level2 PCI intr reg */
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#define VR4122_MPCIINT_REG_W 0x32 /* Level2 PCI intr mask */
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#define VR4181_PCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr reg */
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#define VR4181_MPCIINT_REG_W ICU_NO_REG_W /* Level2 PCI intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define PCIINT_REG_W VR4102_PCIINT_REG_W
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#define MPCIINT_REG_W VR4102_MPCIINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define PCIINT_REG_W VR4122_PCIINT_REG_W
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#define MPCIINT_REG_W VR4122_MPCIINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define PCIINT_REG_W VR4181_PCIINT_REG_W
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#define MPCIINT_REG_W VR4181_MPCIINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define PCIINT_INT0 (1) /* PCI INT 0 */
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/* SCUINT & MSCUINT */
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#define VR4102_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
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#define VR4102_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
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#define VR4122_SCUINT_REG_W 0x2e /* Level2 SCU intr reg */
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#define VR4122_MSCUINT_REG_W 0x34 /* Level2 SCU intr mask */
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#define VR4181_SCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr reg */
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#define VR4181_MSCUINT_REG_W ICU_NO_REG_W /* Level2 SCU intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define SCUINT_REG_W VR4102_SCUINT_REG_W
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#define MSCUINT_REG_W VR4102_MSCUINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define SCUINT_REG_W VR4122_SCUINT_REG_W
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#define MSCUINT_REG_W VR4122_MSCUINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define SCUINT_REG_W VR4181_SCUINT_REG_W
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#define MSCUINT_REG_W VR4181_MSCUINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define SCUINT_INT0 (1) /* SCU INT 0 */
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/* CSIINT & MCSIINT */
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#define VR4102_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
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#define VR4102_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
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#define VR4122_CSIINT_REG_W 0x30 /* Level2 CSI intr reg */
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#define VR4122_MCSIINT_REG_W 0x36 /* Level2 CSI intr mask */
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#define VR4181_CSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr reg */
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#define VR4181_MCSIINT_REG_W ICU_NO_REG_W /* Level2 CSI intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define CSIINT_REG_W VR4102_CSIINT_REG_W
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#define MCSIINT_REG_W VR4102_MCSIINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define CSIINT_REG_W VR4122_CSIINT_REG_W
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#define MCSIINT_REG_W VR4122_MCSIINT_REG_W
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#endif /* VRGROUP_4122_4131 */
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#if defined VRGROUP_4181
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#define CSIINT_REG_W VR4181_CSIINT_REG_W
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#define MCSIINT_REG_W VR4181_MCSIINT_REG_W
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#endif /* VRGROUP_4181 */
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#endif
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#define CSIINT_TRPAGE2 (1<<6) /* DMA send page 2 intr */
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#define CSIINT_TRPAGE1 (1<<5) /* DMA send page 1 intr */
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#define CSIINT_TREND (1<<4) /* send every data intr */
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#define CSIINT_TREMPTY (1<<3) /* send FIFO empty intr */
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#define CSIINT_RCPAGE2 (1<<2) /* DMA recv page 2 intr */
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#define CSIINT_RCPAGE1 (1<<1) /* DMA recv page 1 intr */
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#define CSIINT_RCOVER (1) /* recv FIFO overrun intr */
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/* BCUINT & MBCUINT */
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#define VR4102_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
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#define VR4102_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */
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#define VR4122_BCUINT_REG_W 0x38 /* Level2 BCU intr reg */
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#define VR4122_MBCUINT_REG_W 0x3a /* Level2 BCU intr mask */
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#define VR4181_BCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr reg */
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#define VR4181_MBCUINT_REG_W ICU_NO_REG_W /* Level2 BCU intr mask */
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#if defined SINGLE_VRIP_BASE
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#if defined VRGROUP_4102_4121
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#define BCUINT_REG_W VR4102_BCUINT_REG_W
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#define MBCUINT_REG_W VR4102_MBCUINT_REG_W
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#endif /* VRGROUP_4102_4121 */
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#if defined VRGROUP_4122_4131
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#define BCUINT_REG_W VR4122_BCUINT_REG_W
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#define MBCUINT_REG_W VR4122_MBCUINT_REG_W
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|
#endif /* VRGROUP_4122_4131 */
|
|
#if defined VRGROUP_4181
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|
#define BCUINT_REG_W VR4181_BCUINT_REG_W
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#define MBCUINT_REG_W VR4181_MBCUINT_REG_W
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|
#endif /* VRGROUP_4181 */
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#endif
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#define BCUINT_INT (1) /* BCU INT */
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/* END icureg.h */
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