253 lines
7.0 KiB
C
253 lines
7.0 KiB
C
/* $NetBSD: if_epic_pci.c,v 1.15 2000/12/28 22:59:13 sommerfeld Exp $ */
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/*-
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* Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* PCI bus front-end for the Standard Microsystems Corp. 83C170
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* Ethernet PCI Integrated Controller (EPIC/100) driver.
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*/
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#include "opt_inet.h"
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#include "opt_ns.h"
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#include "bpfilter.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <sys/ioctl.h>
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#include <sys/errno.h>
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#include <sys/device.h>
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#include <net/if.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_ether.h>
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#if NBPFILTER > 0
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#include <net/bpf.h>
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#endif
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#ifdef INET
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#include <netinet/in.h>
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#include <netinet/if_inarp.h>
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#endif
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#ifdef NS
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#include <netns/ns.h>
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#include <netns/ns_if.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/mii/miivar.h>
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#include <dev/ic/smc83c170reg.h>
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#include <dev/ic/smc83c170var.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcidevs.h>
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/*
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* PCI configuration space registers used by the EPIC.
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*/
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#define EPIC_PCI_IOBA 0x10 /* i/o mapped base */
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#define EPIC_PCI_MMBA 0x14 /* memory mapped base */
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struct epic_pci_softc {
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struct epic_softc sc_epic; /* real EPIC softc */
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/* PCI-specific goo. */
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void *sc_ih; /* interrupt handle */
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};
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int epic_pci_match(struct device *, struct cfdata *, void *);
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void epic_pci_attach(struct device *, struct device *, void *);
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struct cfattach epic_pci_ca = {
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sizeof(struct epic_pci_softc), epic_pci_match, epic_pci_attach,
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};
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const struct epic_pci_product {
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u_int32_t epp_prodid; /* PCI product ID */
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const char *epp_name; /* device name */
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} epic_pci_products[] = {
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{ PCI_PRODUCT_SMC_83C170, "SMC 83c170 Fast Ethernet" },
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{ PCI_PRODUCT_SMC_83C175, "SMC 83c175 Fast Ethernet" },
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{ 0, NULL },
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};
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const struct epic_pci_product *epic_pci_lookup(const struct pci_attach_args *);
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const struct epic_pci_product *
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epic_pci_lookup(pa)
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const struct pci_attach_args *pa;
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{
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const struct epic_pci_product *epp;
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if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SMC)
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return (NULL);
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for (epp = epic_pci_products; epp->epp_name != NULL; epp++)
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if (PCI_PRODUCT(pa->pa_id) == epp->epp_prodid)
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return (epp);
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return (NULL);
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}
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int
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epic_pci_match(parent, match, aux)
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struct device *parent;
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struct cfdata *match;
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void *aux;
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{
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struct pci_attach_args *pa = aux;
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if (epic_pci_lookup(pa) != NULL)
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return (1);
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return (0);
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}
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void
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epic_pci_attach(parent, self, aux)
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struct device *parent, *self;
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void *aux;
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{
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struct epic_pci_softc *psc = (struct epic_pci_softc *)self;
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struct epic_softc *sc = &psc->sc_epic;
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struct pci_attach_args *pa = aux;
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pci_chipset_tag_t pc = pa->pa_pc;
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pci_intr_handle_t ih;
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const char *intrstr = NULL;
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const struct epic_pci_product *epp;
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bus_space_tag_t iot, memt;
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bus_space_handle_t ioh, memh;
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pcireg_t reg;
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int pmreg, ioh_valid, memh_valid;
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if (pci_get_capability(pc, pa->pa_tag, PCI_CAP_PWRMGMT, &pmreg, 0)) {
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reg = pci_conf_read(pc, pa->pa_tag, pmreg + 4);
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switch (reg & PCI_PMCSR_STATE_MASK) {
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case PCI_PMCSR_STATE_D1:
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case PCI_PMCSR_STATE_D2:
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printf(": waking up from power state D%d\n%s",
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reg & PCI_PMCSR_STATE_MASK, sc->sc_dev.dv_xname);
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pci_conf_write(pc, pa->pa_tag, pmreg + 4,
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(reg & ~PCI_PMCSR_STATE_MASK) |
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PCI_PMCSR_STATE_D0);
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break;
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case PCI_PMCSR_STATE_D3:
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/*
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* IO and MEM are disabled. We can't enable
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* the card because the BARs might be invalid.
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*/
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printf(": unable to wake up from power state D3, "
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"reboot required.\n");
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pci_conf_write(pc, pa->pa_tag, pmreg + 4,
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(reg & ~PCI_PMCSR_STATE_MASK) |
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PCI_PMCSR_STATE_D0);
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return;
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}
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}
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/*
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* Map the device.
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*/
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ioh_valid = (pci_mapreg_map(pa, EPIC_PCI_IOBA,
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PCI_MAPREG_TYPE_IO, 0,
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&iot, &ioh, NULL, NULL) == 0);
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memh_valid = (pci_mapreg_map(pa, EPIC_PCI_MMBA,
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PCI_MAPREG_TYPE_MEM|PCI_MAPREG_MEM_TYPE_32BIT, 0,
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&memt, &memh, NULL, NULL) == 0);
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if (memh_valid) {
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sc->sc_st = memt;
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sc->sc_sh = memh;
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} else if (ioh_valid) {
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sc->sc_st = iot;
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sc->sc_sh = ioh;
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} else {
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printf(": unable to map device registers\n");
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return;
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}
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sc->sc_dmat = pa->pa_dmat;
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epp = epic_pci_lookup(pa);
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if (epp == NULL) {
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printf("\n");
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panic("epic_pci_attach: impossible");
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}
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printf(": %s, rev. %d\n", epp->epp_name, PCI_REVISION(pa->pa_class));
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/* Make sure bus mastering is enabled. */
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pci_conf_write(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
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pci_conf_read(pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
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PCI_COMMAND_MASTER_ENABLE);
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/*
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* Map and establish our interrupt.
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*/
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if (pci_intr_map(pa, &ih)) {
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printf("%s: unable to map interrupt\n", sc->sc_dev.dv_xname);
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return;
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}
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intrstr = pci_intr_string(pc, ih);
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psc->sc_ih = pci_intr_establish(pc, ih, IPL_NET, epic_intr, sc);
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if (psc->sc_ih == NULL) {
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printf("%s: unable to establish interrupt",
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sc->sc_dev.dv_xname);
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if (intrstr != NULL)
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printf(" at %s", intrstr);
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printf("\n");
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return;
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}
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printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, intrstr);
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/*
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* Finish off the attach.
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*/
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epic_attach(sc);
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}
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