295 lines
8.3 KiB
C
295 lines
8.3 KiB
C
/* $NetBSD: apbus.c,v 1.19 2017/05/19 07:43:31 skrll Exp $ */
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/*-
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* Copyright (c) 2014 Michael Lorenz
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/* catch-all for on-chip peripherals */
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: apbus.c,v 1.19 2017/05/19 07:43:31 skrll Exp $");
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#include "locators.h"
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#define _MIPS_BUS_DMA_PRIVATE
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/device.h>
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#include <sys/extent.h>
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#include <sys/systm.h>
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#include <mips/ingenic/ingenic_var.h>
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#include <mips/ingenic/ingenic_regs.h>
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#include "opt_ingenic.h"
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static int apbus_match(device_t, cfdata_t, void *);
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static void apbus_attach(device_t, device_t, void *);
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static int apbus_print(void *, const char *);
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static void apbus_bus_mem_init(bus_space_tag_t, void *);
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CFATTACH_DECL_NEW(apbus, 0, apbus_match, apbus_attach, NULL, NULL);
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static struct mips_bus_space apbus_mbst;
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bus_space_tag_t apbus_memt = NULL;
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struct mips_bus_dma_tag apbus_dmat = {
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._bounce_alloc_hi = 0x10000000,
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._dmamap_ops = _BUS_DMAMAP_OPS_INITIALIZER,
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._dmamem_ops = _BUS_DMAMEM_OPS_INITIALIZER,
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._dmatag_ops = _BUS_DMATAG_OPS_INITIALIZER,
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};
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typedef struct apbus_dev {
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const char *name; /* driver name */
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bus_addr_t addr; /* base address */
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uint32_t irq; /* interrupt */
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uint32_t clk0; /* bit(s) in CLKGR0 */
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uint32_t clk1; /* bit(s) in CLKGR1 */
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uint32_t clkreg; /* CGU register */
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} apbus_dev_t;
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static const apbus_dev_t apbus_devs[] = {
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{ "efuse", JZ_EFUSE, -1, 0, 0, 0},
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{ "com", JZ_UART0, 51, CLK_UART0, 0, 0},
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{ "com", JZ_UART1, 50, CLK_UART1, 0, 0},
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{ "com", JZ_UART2, 49, CLK_UART2, 0, 0},
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{ "com", JZ_UART3, 48, CLK_UART3, 0, 0},
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{ "com", JZ_UART4, 34, 0, CLK_UART4, 0},
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{ "dwctwo", JZ_DWC2_BASE, 21, CLK_OTG0 | CLK_UHC, CLK_OTG1, 0},
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{ "ohci", JZ_OHCI_BASE, 5, CLK_UHC, 0, 0},
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{ "ehci", JZ_EHCI_BASE, 20, CLK_UHC, 0, 0},
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{ "dme", JZ_DME_BASE, -1, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_A_BASE, 17, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_B_BASE, 16, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_C_BASE, 15, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_D_BASE, 14, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_E_BASE, 13, 0, 0, 0},
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{ "jzgpio", JZ_GPIO_F_BASE, 12, 0, 0, 0},
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{ "jziic", JZ_SMB0_BASE, 60, CLK_SMB0, 0, 0},
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{ "jziic", JZ_SMB1_BASE, 59, CLK_SMB1, 0, 0},
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{ "jziic", JZ_SMB2_BASE, 58, CLK_SMB2, 0, 0},
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{ "jziic", JZ_SMB3_BASE, 57, 0, CLK_SMB3, 0},
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{ "jziic", JZ_SMB4_BASE, 56, 0, CLK_SMB4, 0},
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{ "jzmmc", JZ_MSC0_BASE, 37, CLK_MSC0, 0, JZ_MSC0CDR},
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{ "jzmmc", JZ_MSC1_BASE, 36, CLK_MSC1, 0, JZ_MSC1CDR},
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{ "jzmmc", JZ_MSC2_BASE, 35, CLK_MSC2, 0, JZ_MSC2CDR},
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{ "jzfb", JZ_LCDC0_BASE, 31, CLK_LCD, CLK_HDMI, 0},
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{ "jzrng", JZ_RNG, -1, 0, 0, 0},
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{ NULL, -1, -1, 0, 0, 0}
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};
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void
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apbus_init(void)
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{
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static bool done = false;
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if (done)
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return;
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done = true;
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apbus_bus_mem_init(&apbus_mbst, NULL);
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apbus_memt = &apbus_mbst;
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}
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int
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apbus_match(device_t parent, cfdata_t match, void *aux)
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{
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struct mainbusdev {
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const char *md_name;
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} *aa = aux;
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if (strcmp(aa->md_name, "apbus") == 0) return 1;
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return 0;
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}
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void
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apbus_attach(device_t parent, device_t self, void *aux)
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{
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uint32_t reg, mpll, m, n, p, mclk, pclk, pdiv, cclk, cdiv;
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aprint_normal("\n");
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/* should have been called early on */
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apbus_init();
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#ifdef INGENIC_DEBUG
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printf("core ctrl: %08x\n", MFC0(12, 2));
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printf("core status: %08x\n", MFC0(12, 3));
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printf("REIM: %08x\n", MFC0(12, 4));
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printf("ID: %08x\n", MFC0(15, 1));
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#endif
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/* assuming we're using MPLL */
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mpll = readreg(JZ_CPMPCR);
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m = (mpll & JZ_PLLM_M) >> JZ_PLLM_S;
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n = (mpll & JZ_PLLN_M) >> JZ_PLLN_S;
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p = (mpll & JZ_PLLP_M) >> JZ_PLLP_S;
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/* assuming 48MHz EXTCLK */
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mclk = (48000 * (m + 1) / (n + 1)) / (p + 1);
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reg = readreg(JZ_CPCCR);
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pdiv = ((reg & JZ_PDIV_M) >> JZ_PDIV_S) + 1;
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pclk = mclk / pdiv;
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cdiv = (reg & JZ_CDIV_M) + 1;
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cclk = mclk / cdiv;
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aprint_debug_dev(self, "mclk %d kHz\n", mclk);
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aprint_debug_dev(self, "pclk %d kHz\n", pclk);
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aprint_debug_dev(self, "CPU clock %d kHz\n", cclk);
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/* enable clocks */
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reg = readreg(JZ_CLKGR1);
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reg &= ~CLK_AHB_MON; /* AHB_MON clock */
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writereg(JZ_CLKGR1, reg);
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/* enable RNG */
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writereg(JZ_ERNG, 1);
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/* wake up the USB part */
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reg = readreg(JZ_OPCR);
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reg |= OPCR_SPENDN0 | OPCR_SPENDN1;
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writereg(JZ_OPCR, reg);
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/* wire up GPIOs */
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/* iic0 */
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gpio_as_dev0(3, 30);
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gpio_as_dev0(3, 31);
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/* iic1 */
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gpio_as_dev0(4, 30);
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gpio_as_dev0(4, 31);
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/* iic2 */
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gpio_as_dev2(5, 16);
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gpio_as_dev2(5, 17);
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/* iic3 */
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gpio_as_dev1(3, 10);
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gpio_as_dev1(3, 11);
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/* iic4 */
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/* make sure these aren't SMB4 */
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gpio_as_dev3(4, 3);
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gpio_as_dev3(4, 4);
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/* these are supposed to be connected to the RTC */
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gpio_as_dev1(4, 12);
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gpio_as_dev1(4, 13);
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/* these can be DDC2 or SMB4 */
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#if 0
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/* DDC2 devices show up at SMB4 */
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gpio_as_dev1(5, 24);
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gpio_as_dev1(5, 25);
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#else
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gpio_as_dev0(5, 24);
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gpio_as_dev0(5, 25);
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#endif
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/* MSC0 */
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gpio_as_dev1(0, 4);
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gpio_as_dev1(0, 5);
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gpio_as_dev1(0, 6);
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gpio_as_dev1(0, 7);
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gpio_as_dev1(0, 18);
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gpio_as_dev1(0, 19);
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gpio_as_dev1(0, 20);
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gpio_as_dev1(0, 21);
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gpio_as_dev1(0, 22);
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gpio_as_dev1(0, 23);
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gpio_as_dev1(0, 24);
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gpio_as_intr_level_low(5, 20); /* card detect */
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/* MSC1, for wifi/bt */
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gpio_as_dev0(3, 20);
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gpio_as_dev0(3, 21);
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gpio_as_dev0(3, 22);
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gpio_as_dev0(3, 23);
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gpio_as_dev0(3, 24);
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gpio_as_dev0(3, 25);
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/* MSC2, on expansion header */
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gpio_as_dev0(1, 20);
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gpio_as_dev0(1, 21);
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gpio_as_dev0(1, 28);
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gpio_as_dev0(1, 29);
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gpio_as_dev0(1, 30);
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gpio_as_dev0(1, 31);
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#ifndef INGENIC_DEBUG
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printf("JZ_CLKGR0 %08x\n", readreg(JZ_CLKGR0));
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printf("JZ_CLKGR1 %08x\n", readreg(JZ_CLKGR1));
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printf("JZ_SPCR0 %08x\n", readreg(JZ_SPCR0));
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printf("JZ_SPCR1 %08x\n", readreg(JZ_SPCR1));
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printf("JZ_SRBC %08x\n", readreg(JZ_SRBC));
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printf("JZ_OPCR %08x\n", readreg(JZ_OPCR));
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printf("JZ_UHCCDR %08x\n", readreg(JZ_UHCCDR));
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printf("JZ_ERNG %08x\n", readreg(JZ_ERNG));
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printf("JZ_RNG %08x\n", readreg(JZ_RNG));
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#endif
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for (const apbus_dev_t *adv = apbus_devs; adv->name != NULL; adv++) {
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struct apbus_attach_args aa;
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aa.aa_name = adv->name;
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aa.aa_addr = adv->addr;
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aa.aa_irq = adv->irq;
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aa.aa_dmat = &apbus_dmat;
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aa.aa_bst = apbus_memt;
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aa.aa_pclk = pclk;
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aa.aa_mclk = mclk;
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aa.aa_clockreg = adv->clkreg;
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/* enable clocks as needed */
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if (adv->clk0 != 0) {
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reg = readreg(JZ_CLKGR0);
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reg &= ~adv->clk0;
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writereg(JZ_CLKGR0, reg);
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}
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if (adv->clk1 != 0) {
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reg = readreg(JZ_CLKGR1);
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reg &= ~adv->clk1;
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writereg(JZ_CLKGR1, reg);
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}
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(void) config_found_ia(self, "apbus", &aa, apbus_print);
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}
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}
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int
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apbus_print(void *aux, const char *pnp)
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{
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struct apbus_attach_args *aa = aux;
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if (pnp) {
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aprint_normal("%s at %s", aa->aa_name, pnp);
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}
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if (aa->aa_addr != -1)
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aprint_normal(" addr 0x%" PRIxBUSADDR, aa->aa_addr);
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if ((pnp == NULL) && (aa->aa_irq != -1))
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aprint_normal(" irq %d", aa->aa_irq);
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return (UNCONF);
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}
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#define CHIP apbus
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#define CHIP_MEM /* defined */
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#define CHIP_W1_BUS_START(v) 0x10000000UL
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#define CHIP_W1_BUS_END(v) 0x20000000UL
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#define CHIP_W1_SYS_START(v) 0x10000000UL
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#define CHIP_W1_SYS_END(v) 0x20000000UL
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#include <mips/mips/bus_space_alignstride_chipdep.c>
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