269 lines
6.9 KiB
C
269 lines
6.9 KiB
C
/* $NetBSD: fdt_clock.c,v 1.10 2019/11/09 23:28:26 jmcneill Exp $ */
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/*-
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* Copyright (c) 2015 Jared D. McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__KERNEL_RCSID(0, "$NetBSD: fdt_clock.c,v 1.10 2019/11/09 23:28:26 jmcneill Exp $");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kmem.h>
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#include <sys/queue.h>
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#include <libfdt.h>
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#include <dev/fdt/fdtvar.h>
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#include <dev/clk/clk_backend.h>
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struct fdtbus_clock_controller {
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device_t cc_dev;
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int cc_phandle;
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const struct fdtbus_clock_controller_func *cc_funcs;
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LIST_ENTRY(fdtbus_clock_controller) cc_next;
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};
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static LIST_HEAD(, fdtbus_clock_controller) fdtbus_clock_controllers =
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LIST_HEAD_INITIALIZER(fdtbus_clock_controller);
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int
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fdtbus_register_clock_controller(device_t dev, int phandle,
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const struct fdtbus_clock_controller_func *funcs)
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{
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struct fdtbus_clock_controller *cc;
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cc = kmem_alloc(sizeof(*cc), KM_SLEEP);
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cc->cc_dev = dev;
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cc->cc_phandle = phandle;
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cc->cc_funcs = funcs;
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LIST_INSERT_HEAD(&fdtbus_clock_controllers, cc, cc_next);
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fdtbus_clock_assign(phandle);
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return 0;
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}
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static struct fdtbus_clock_controller *
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fdtbus_get_clock_controller(int phandle)
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{
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struct fdtbus_clock_controller *cc;
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LIST_FOREACH(cc, &fdtbus_clock_controllers, cc_next) {
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if (cc->cc_phandle == phandle)
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return cc;
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}
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return NULL;
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}
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static struct clk *
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fdtbus_clock_get_index_prop(int phandle, u_int index, const char *prop)
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{
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struct fdtbus_clock_controller *cc;
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struct clk *clk = NULL;
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const u_int *p;
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u_int n, clock_cells;
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int len, resid;
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p = fdtbus_get_prop(phandle, prop, &len);
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if (p == NULL)
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return NULL;
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for (n = 0, resid = len; resid > 0; n++) {
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const int cc_phandle =
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fdtbus_get_phandle_from_native(be32toh(p[0]));
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if (of_getprop_uint32(cc_phandle, "#clock-cells", &clock_cells))
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break;
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if (n == index) {
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cc = fdtbus_get_clock_controller(cc_phandle);
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if (cc == NULL)
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break;
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clk = cc->cc_funcs->decode(cc->cc_dev, cc_phandle,
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clock_cells > 0 ? &p[1] : NULL, clock_cells * 4);
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break;
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}
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resid -= (clock_cells + 1) * 4;
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p += clock_cells + 1;
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}
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return clk;
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}
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struct clk *
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fdtbus_clock_get_index(int phandle, u_int index)
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{
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return fdtbus_clock_get_index_prop(phandle, index, "clocks");
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}
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static struct clk *
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fdtbus_clock_get_prop(int phandle, const char *clkname, const char *prop)
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{
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u_int index;
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int err;
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err = fdtbus_get_index(phandle, prop, clkname, &index);
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if (err != 0)
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return NULL;
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return fdtbus_clock_get_index(phandle, index);
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}
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u_int
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fdtbus_clock_count(int phandle, const char *prop)
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{
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u_int n, clock_cells;
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int len, resid;
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const u_int *p = fdtbus_get_prop(phandle, prop, &len);
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if (p == NULL)
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return 0;
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for (n = 0, resid = len; resid > 0; n++) {
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const int cc_phandle =
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fdtbus_get_phandle_from_native(be32toh(p[0]));
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if (of_getprop_uint32(cc_phandle, "#clock-cells", &clock_cells))
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break;
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resid -= (clock_cells + 1) * 4;
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p += clock_cells + 1;
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}
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return n;
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}
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struct clk *
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fdtbus_clock_get(int phandle, const char *clkname)
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{
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return fdtbus_clock_get_prop(phandle, clkname, "clock-names");
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}
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int
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fdtbus_clock_enable(int phandle, const char *clkname, bool required)
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{
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struct clk *clk;
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clk = fdtbus_clock_get(phandle, clkname);
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if (clk == NULL)
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return required ? ENOENT : 0;
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return clk_enable(clk);
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}
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int
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fdtbus_clock_enable_index(int phandle, u_int index, bool required)
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{
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struct clk *clk;
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clk = fdtbus_clock_get_index(phandle, index);
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if (clk == NULL)
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return required ? ENOENT : 0;
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return clk_enable(clk);
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}
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/*
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* Search the DT for a clock by "clock-output-names" property.
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*
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* This should only be used by clk backends. Not for use by ordinary
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* clock consumers!
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*/
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struct clk *
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fdtbus_clock_byname(const char *clkname)
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{
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struct fdtbus_clock_controller *cc;
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u_int index, clock_cells;
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int err;
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LIST_FOREACH(cc, &fdtbus_clock_controllers, cc_next) {
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err = fdtbus_get_index(cc->cc_phandle, "clock-output-names", clkname, &index);
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if (err != 0)
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continue;
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if (of_getprop_uint32(cc->cc_phandle, "#clock-cells", &clock_cells))
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continue;
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const u_int index_raw = htobe32(index);
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return cc->cc_funcs->decode(cc->cc_dev,
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cc->cc_phandle,
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clock_cells > 0 ? &index_raw : NULL,
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clock_cells > 0 ? 4 : 0);
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}
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return NULL;
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}
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/*
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* Apply assigned clock parents and rates.
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*
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* This is automatically called by fdtbus_register_clock_controller, so clock
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* drivers likely don't need to call this directly.
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*/
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void
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fdtbus_clock_assign(int phandle)
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{
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u_int index, rates_len;
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struct clk *clk, *clk_parent;
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int error;
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const u_int *rates = fdtbus_get_prop(phandle, "assigned-clock-rates", &rates_len);
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if (rates == NULL)
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rates_len = 0;
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const u_int nclocks = fdtbus_clock_count(phandle, "assigned-clocks");
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const u_int nparents = fdtbus_clock_count(phandle, "assigned-clock-parents");
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const u_int nrates = rates_len / sizeof(*rates);
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for (index = 0; index < nclocks; index++) {
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clk = fdtbus_clock_get_index_prop(phandle, index, "assigned-clocks");
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if (clk == NULL) {
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aprint_debug("clk: assigned clock (%u) not found, skipping...\n", index);
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continue;
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}
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if (index < nparents) {
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clk_parent = fdtbus_clock_get_index_prop(phandle, index, "assigned-clock-parents");
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if (clk_parent != NULL) {
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error = clk_set_parent(clk, clk_parent);
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if (error != 0) {
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aprint_error("clk: failed to set %s parent to %s, error %d\n",
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clk->name, clk_parent->name, error);
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}
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} else {
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aprint_debug("clk: failed to set %s parent (not found)\n", clk->name);
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}
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}
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if (index < nrates) {
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const u_int rate = be32toh(rates[index]);
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if (rate != 0) {
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error = clk_set_rate(clk, rate);
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if (error != 0)
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aprint_error("clk: failed to set %s rate to %u Hz, error %d\n",
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clk->name, rate, error);
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}
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}
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}
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}
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