bd5cb77445
Tested on Intel SS4200-E (ICH7), and Acorp 6A815EPD (ICH2) motherboards, on amd64 and i386 ports respectively. It should be noted that the majority of boards with ICH chips do not expose the GPIO pins for off-board use. For instance, aside from the three exposed-on-a-header pins on the 6A815EPD, another pin is also used to control write protect on the FWH. The SS4200 exposes the GPIO on a header that connects to the 10 LEDs on the front panel, as well as a tact switch on the back panel.
301 lines
12 KiB
C
301 lines
12 KiB
C
/* $NetBSD: i82801lpcreg.h,v 1.10 2009/09/27 17:55:32 jakllsch Exp $ */
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/*-
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* Copyright (c) 2004 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Minoura Makoto.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part
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* register definitions.
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*/
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#ifndef _DEV_IC_I82801LPGREG_H_
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#define _DEV_IC_I82801LPGREG_H_
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/*
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* PCI configuration registers
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*/
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#define LPCIB_PCI_PMBASE 0x40
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#define LPCIB_PCI_ACPI_CNTL 0x44
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# define LPCIB_PCI_ACPI_CNTL_EN (1 << 4)
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/* GPIO config registers ICH6+ */
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#define LPCIB_PCI_GPIO_BASE_ICH6 0x48
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#define LPCIB_PCI_GPIO_CNTL_ICH6 0x4c
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#define LPCIB_PCI_BIOS_CNTL 0x4e
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#define LPCIB_PCI_TCO_CNTL 0x54
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/* GPIO config registers ICH0-ICH5 */
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#define LPCIB_PCI_GPIO_BASE 0x58
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#define LPCIB_PCI_GPIO_CNTL 0x5c
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#define LPCIB_PCI_GPIO_CNTL_EN (1 << 4)
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#define LPCIB_PCI_PIRQA_ROUT 0x60
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#define LPCIB_PCI_PIRQB_ROUT 0x61
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#define LPCIB_PCI_PIRQC_ROUT 0x62
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#define LPCIB_PCI_PIRQD_ROUT 0x63
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#define LPCIB_PCI_SIRQ_CNTL 0x64
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#define LPCIB_PCI_PIRQE_ROUT 0x68
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#define LPCIB_PCI_PIRQF_ROUT 0x69
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#define LPCIB_PCI_PIRQG_ROUT 0x6a
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#define LPCIB_PCI_PIRQH_ROUT 0x6b
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#define LPCIB_PCI_D31_ERR_CFG 0x88
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#define LPCIB_PCI_D31_ERR_STS 0x8a
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#define LPCIB_PCI_PCI_DMA_C 0x90
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#define LPCIB_PCI_GEN_PMCON_1 0xa0
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# define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08
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#define LPCIB_PCI_GEN_PMCON_2 0xa2
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#define LPCIB_PCI_GEN_PMCON_3 0xa4
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#define LPCIB_PCI_STPCLK_DEL 0xa8
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#define LPCIB_PCI_GPI_ROUT 0xb8
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#define LPCIB_PCI_TRP_FWD_EN 0xc0
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#define LPCIB_PCI_MON4_TRP_RNG 0xc4
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#define LPCIB_PCI_MON5_TRP_RNG 0xc5
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#define LPCIB_PCI_MON6_TRP_RNG 0xc6
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#define LPCIB_PCI_MON7_TRP_RNG 0xc7
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#define LPCIB_PCI_MON_TRP_MSK 0xcc
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#define LPCIB_PCI_GEN_CNTL 0xd0
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#define LPCIB_ICH5_HPTC_EN 0x00020000
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#define LPCIB_ICH5_HPTC_WIN_MASK 0x0000c000
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#define LPCIB_ICH5_HPTC_0000 0x00000000
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#define LPCIB_ICH5_HPTC_0000_BASE 0xfed00000
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#define LPCIB_ICH5_HPTC_1000 0x00008000
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#define LPCIB_ICH5_HPTC_1000_BASE 0xfed01000
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#define LPCIB_ICH5_HPTC_2000 0x00010000
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#define LPCIB_ICH5_HPTC_2000_BASE 0xfed02000
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#define LPCIB_ICH5_HPTC_3000 0x00018000
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#define LPCIB_ICH5_HPTC_3000_BASE 0xfed03000
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#define LPCIB_PCI_GEN_STA 0xd4
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# define LPCIB_PCI_GEN_STA_SAFE_MODE (1 << 2)
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# define LPCIB_PCI_GEN_STA_NO_REBOOT (1 << 1)
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#define LPCIB_PCI_BACK_CNTL 0xd5
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#define LPCIB_PCI_RTC_CONF 0xd8
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#define LPCIB_PCI_COM_DEC 0xe0
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#define LPCIB_PCI_LPCFDD_DEC 0xe1
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#define LPCIB_PCI_SND_DEC 0xe2
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#define LPCIB_PCI_FWH_DEC_EN1 0xe3
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#define LPCIB_PCI_GEN1_DEC 0xe4
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#define LPCIB_PCI_LPC_EN 0xe6
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#define LPCIB_PCI_FWH_SEL1 0xe8
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#define LPCIB_PCI_GEN2_DEC 0xec
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#define LPCIB_PCI_FWH_SEL2 0xee
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#define LPCIB_PCI_FWH_DEC_EN2 0xf0
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#define LPCIB_PCI_FUNC_DIS 0xf2
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/*
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* Power management I/O registers
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* (offset from PMBASE)
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*/
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#define LPCIB_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */
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#define LPCIB_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */
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#define LPCIB_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */
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#define LPCIB_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */
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#define LPCIB_PROC_CNT 0x10 /* ACPI P_BLK processor control */
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#define LPCIB_LV2 0x14 /* ACPI P_BLK processor C2 control */
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#define LPCIB_PM_CTRL 0x20 /* ACPI Power Management Control */
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# define LPCIB_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */
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#define LPCIB_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */
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#define LPCIB_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */
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#define LPCIB_SMI_EN 0x30
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# define LPCIB_SMI_EN_INTEL_USB2_EN (1 << 18)
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# define LPCIB_SMI_EN_LEGACY_USB2_EN (1 << 17)
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# define LPCIB_SMI_EN_PERIODIC_EN (1 << 14)
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# define LPCIB_SMI_EN_TCO_EN (1 << 13)
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# define LPCIB_SMI_EN_MCSMI_EN (1 << 11)
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# define LPCIB_SMI_EN_BIOS_RLS (1 << 7)
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# define LPCIB_SMI_EN_SWSMI_TMR_EN (1 << 6)
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# define LPCIB_SMI_EN_APMC_EN (1 << 5)
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# define LPCIB_SMI_EN_SLP_SMI_EN (1 << 4)
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# define LPCIB_SMI_EN_LEGACY_USB_EN (1 << 3)
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# define LPCIB_SMI_EN_BIOS_EN (1 << 2)
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# define LPCIB_SMI_EN_EOS (1 << 1)
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# define LPCIB_SMI_EN_GBL_SMI_EN (1 << 0)
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#define LPCIB_SMI_STS 0x34
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#define LPCIB_ALT_GP_SMI_EN 0x38
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#define LPCIB_ALT_GP_SMI_STS 0x3a
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#define LPCIB_MON_SMI 0x40
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#define LPCIB_DEVACT_STS 0x44
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#define LPCIB_DEVTRAP_EN 0x48
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#define LPCIB_BUS_ADDR_TRACK 0x4c
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#define LPCIB_BUS_CYC_TRACK 0x4e
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#define LPCIB_PM_SS_CNTL 0x50 /* SpeedStep control */
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# define LPCIB_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */
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/*
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* General Purpose I/O Registers
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* (offset from GPIO_BASE)
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*/
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#define LPCIB_GPIO_GPIO_USE_SEL 0x00
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#define LPCIB_GPIO_GP_IO_SEL 0x04
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#define LPCIB_GPIO_GP_LVL 0x0c
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#define LPCIB_GPIO_GPO_TTL 0x14
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#define LPCIB_GPIO_GPO_BLINK 0x18
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#define LPCIB_GPIO_GPI_INV 0x2c
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#define LPCIB_GPIO_GPIO_USE_SEL2 0x30
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#define LPCIB_GPIO_GP_IO_SEL2 0x34
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#define LPCIB_GPIO_GP_LVL2 0x38
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/*
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* SMBus controller registers.
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*/
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/* PCI configuration registers */
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#define LPCIB_SMB_BASE 0x20 /* SMBus base address */
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#define LPCIB_SMB_HOSTC 0x40 /* host configuration */
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#define LPCIB_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */
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#define LPCIB_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */
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#define LPCIB_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */
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/* SMBus I/O registers */
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#define LPCIB_SMB_HS 0x00 /* host status */
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#define LPCIB_SMB_HS_BUSY (1 << 0) /* running a command */
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#define LPCIB_SMB_HS_INTR (1 << 1) /* command completed */
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#define LPCIB_SMB_HS_DEVERR (1 << 2) /* command error */
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#define LPCIB_SMB_HS_BUSERR (1 << 3) /* transaction collision */
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#define LPCIB_SMB_HS_FAILED (1 << 4) /* failed bus transaction */
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#define LPCIB_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */
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#define LPCIB_SMB_HS_INUSE (1 << 6) /* bus semaphore */
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#define LPCIB_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */
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#define LPCIB_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE"
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#define LPCIB_SMB_HC 0x02 /* host control */
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#define LPCIB_SMB_HC_INTREN (1 << 0) /* enable interrupts */
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#define LPCIB_SMB_HC_KILL (1 << 1) /* kill current transaction */
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#define LPCIB_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */
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#define LPCIB_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */
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#define LPCIB_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */
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#define LPCIB_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */
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#define LPCIB_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */
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#define LPCIB_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */
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#define LPCIB_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */
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#define LPCIB_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */
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#define LPCIB_SMB_HC_LASTB (1 << 5) /* last byte in block */
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#define LPCIB_SMB_HC_START (1 << 6) /* start transaction */
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#define LPCIB_SMB_HC_PECEN (1 << 7) /* enable PEC */
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#define LPCIB_SMB_HCMD 0x03 /* host command */
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#define LPCIB_SMB_TXSLVA 0x04 /* transmit slave address */
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#define LPCIB_SMB_TXSLVA_READ (1 << 0) /* read direction */
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#define LPCIB_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */
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#define LPCIB_SMB_HD0 0x05 /* host data 0 */
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#define LPCIB_SMB_HD1 0x06 /* host data 1 */
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#define LPCIB_SMB_HBDB 0x07 /* host block data byte */
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#define LPCIB_SMB_PEC 0x08 /* PEC data */
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#define LPCIB_SMB_RXSLVA 0x09 /* receive slave address */
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#define LPCIB_SMB_SD 0x0a /* receive slave data */
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#define LPCIB_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */
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#define LPCIB_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */
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#define LPCIB_SMB_AS 0x0c /* auxiliary status */
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#define LPCIB_SMB_AS_CRCE (1 << 0) /* CRC error */
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#define LPCIB_SMB_AS_TCO (1 << 1) /* advanced TCO mode */
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#define LPCIB_SMB_AC 0x0d /* auxiliary control */
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#define LPCIB_SMB_AC_AAC (1 << 0) /* automatically append CRC */
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#define LPCIB_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */
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#define LPCIB_SMB_SMLPC 0x0e /* SMLink pin control */
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#define LPCIB_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */
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#define LPCIB_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */
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#define LPCIB_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */
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#define LPCIB_SMB_SMBPC 0x0f /* SMBus pin control */
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#define LPCIB_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */
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#define LPCIB_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */
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#define LPCIB_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */
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#define LPCIB_SMB_SS 0x10 /* slave status */
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#define LPCIB_SMB_SS_HN (1 << 0) /* Host Notify command */
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#define LPCIB_SMB_SCMD 0x11 /* slave command */
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#define LPCIB_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */
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#define LPCIB_SMB_SCMD_WKEN (1 << 1) /* wake on HN */
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#define LPCIB_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */
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#define LPCIB_SMB_NDADDR 0x14 /* notify device address */
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#define LPCIB_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */
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#define LPCIB_SMB_NDLOW 0x16 /* notify data low byte */
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#define LPCIB_SMB_NDHIGH 0x17 /* notify data high byte */
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/* ICH Chipset Configuration Registers (ICH6 and newer) */
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#define LPCIB_RCBA 0xf0
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#define LPCIB_RCBA_EN 0x00000001
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#define LPCIB_RCBA_SIZE 0x00004000
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#define LPCIB_GCS_OFFSET 0x3410
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#define LPCIB_GCS_NO_REBOOT 0x20
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#define LPCIB_RCBA_HPTC 0x00003404
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#define LPCIB_RCBA_HPTC_EN 0x00000080
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#define LPCIB_RCBA_HPTC_WIN_MASK 0x00000003
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#define LPCIB_RCBA_HPTC_0000 0x00000000
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#define LPCIB_RCBA_HPTC_0000_BASE 0xfed00000
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#define LPCIB_RCBA_HPTC_1000 0x00000001
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#define LPCIB_RCBA_HPTC_1000_BASE 0xfed01000
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#define LPCIB_RCBA_HPTC_2000 0x00000002
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#define LPCIB_RCBA_HPTC_2000_BASE 0xfed02000
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#define LPCIB_RCBA_HPTC_3000 0x00000003
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#define LPCIB_RCBA_HPTC_3000_BASE 0xfed03000
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/*
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* System management TCO registers
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* (offset from PMBASE)
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*/
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#define LPCIB_TCO_BASE 0x60
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#define LPCIB_TCO_RLD (LPCIB_TCO_BASE+0x00)
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#define LPCIB_TCO_TMR (LPCIB_TCO_BASE+0x01)
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#define LPCIB_TCO_TMR2 (LPCIB_TCO_BASE+0x12) /* ICH6 and newer */
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# define LPCIB_TCO_TMR_MASK 0x3f
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#define LPCIB_TCO_DAT_IN (LPCIB_TCO_BASE+0x02)
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#define LPCIB_TCO_DAT_OUT (LPCIB_TCO_BASE+0x03)
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#define LPCIB_TCO1_STS (LPCIB_TCO_BASE+0x04)
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# define LPCIB_TCO1_STS_TIMEOUT 0x08
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#define LPCIB_TCO2_STS (LPCIB_TCO_BASE+0x06)
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# define LPCIB_TCO2_STS_BOOT_STS 0x04
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# define LPCIB_TCO2_STS_SECONDS_TO_STS 0x02
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#define LPCIB_TCO1_CNT (LPCIB_TCO_BASE+0x08)
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# define LPCIB_TCO1_CNT_TCO_LOCK (1 << 12)
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# define LPCIB_TCO1_CNT_TCO_TMR_HLT (1 << 11)
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# define LPCIB_TCO1_CNT_SEND_NOW (1 << 10)
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# define LPCIB_TCO1_CNT_NMI2SMI_EN (1 << 9)
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# define LPCIB_TCO1_CNT_NMI_NOW (1 << 8)
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#define LPCIB_TCO2_CNT (LPCIB_TCO_BASE+0x0a)
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#define LPCIB_TCO_MESSAGE1 (LPCIB_TCO_BASE+0x0c)
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#define LPCIB_TCO_MESSAGE2 (LPCIB_TCO_BASE+0x0d)
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#define LPCIB_TCO_WDSTATUS (LPCIB_TCO_BASE+0x0e)
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#define LPCIB_SW_IRQ_GEN (LPCIB_TCO_BASE+0x10)
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/*
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* TCO timer tick. ICH datasheets say:
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* - The timer is clocked at approximately 0.6 seconds
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* - 6 bit; values of 0-3 will be ignored and should not be attempted
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*/
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static __inline int
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lpcib_tcotimer_tick_to_second(int ltick)
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{
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return ltick * 6 / 10;
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}
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static __inline int
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lpcib_tcotimer_second_to_tick(int ltick)
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{
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return ltick * 10 / 6;
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}
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#define LPCIB_TCOTIMER_MIN_TICK 4
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#define LPCIB_TCOTIMER2_MIN_TICK 2
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#define LPCIB_TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */
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#define LPCIB_TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */
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#endif /* _DEV_IC_I82801LPGREG_H_ */
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