3111a2e6ea
The driver is not too heavily tested and only supports audio playback and master volume setting currently.
80 lines
2.7 KiB
C
80 lines
2.7 KiB
C
/* $NetBSD: haltworeg.h,v 1.1 2003/09/25 16:35:50 lonewolf Exp $ */
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/*
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* Copyright (c) 2003 Ilpo Ruotsalainen
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* <<Id: LICENSE_GC,v 1.1 2001/10/01 23:24:05 cgd Exp>>
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*/
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#ifndef _ARCH_SGIMIPS_HPC_HALTWOREG_H_
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#define _ARCH_SGIMIPS_HPC_HALTWOREG_H_
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/* HAL2 direct-addressable registers, PBUS PIO channel 0 */
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#define HAL2_REG_CTL_ISR 0x10
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#define HAL2_REG_CTL_REV 0x20
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#define HAL2_REV_AUDIO_PRESENT_N 0x8000
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#define HAL2_REG_CTL_IAR 0x30
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#define HAL2_IAR_READ 0x0080
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#define HAL2_REG_CTL_IDR0 0x40
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#define HAL2_REG_CTL_IDR1 0x50
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#define HAL2_REG_CTL_IDR2 0x60
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#define HAL2_REG_CTL_IDR3 0x70
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#define HAL2_ISR_TSTATUS 0x01
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#define HAL2_ISR_GLOBAL_RESET_N 0x08
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#define HAL2_ISR_CODEC_RESET_N 0x10
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/* HAL2 direct-addressable registers, PBUS PIO channel 2 */
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#define HAL2_REG_VOL_RIGHT 0x00
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#define HAL2_REG_VOL_LEFT 0x04
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/* HAL2 indirect-addressable registers */
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#define HAL2_IREG_RELAY_C 0x9100
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#define HAL2_RELAY_C_STATE 0x01
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#define HAL2_IREG_DMA_PORT_EN 0x9104
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#define HAL2_DMA_PORT_EN_CODECTX 0x08
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#define HAL2_IREG_DMA_END 0x9108
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#define HAL2_DMA_END_CODECTX 0x08
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#define HAL2_IREG_DMA_DRV 0x910C
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#define HAL2_IREG_BRES1_C1 0x2104
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#define HAL2_IREG_BRES1_C2 0x2108
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#define HAL2_IREG_DAC_C1 0x1404
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#define HAL2_C1_DMA_SHIFT 0
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#define HAL2_C1_CLKID_SHIFT 3
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#define HAL2_C1_DATAT_SHIFT 8
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#define HAL2_IREG_DAC_C2 0x1408
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#endif
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